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gameboy sound emulation by blargg

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Jun 21st, 2012
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  1. Game Boy Sound Operation
  2. ------------------------
  3. Shay Green (blargg)
  4. gblargg@gmail.com
  5. http://www.slack.net/~ant/
  6.  
  7. ** This is an incomplete draft
  8.  
  9. This documents the behavior of Game Boy sound; details which aren't
  10. relevant to the observable behavior have been omitted unless they
  11. clarify understanding. It is aimed at answering all questions about
  12. exact operation, rather than describing how to use sound effectively in
  13. Game Boy programs. Values in hexadecimal (base 16) are generally written
  14. with a $ prefix. Bits are numbered from 0 to 7, where bit N has a weight
  15. of 2^N. A nybble is 4 bits, half a byte. Obscure behavior is described
  16. separately to increase clarity elsewhere.
  17.  
  18. Contact me for a set of test ROMs that verify most behavior described
  19. here.
  20.  
  21.  
  22. Contents
  23. --------
  24. - Overview
  25. - Registers
  26. - Channels
  27. - Timer
  28. - Frame Sequencer
  29. - Length Counter
  30. - Volume Envelope
  31. - Square Wave
  32. - Frequency Sweep
  33. - Noise Channel
  34. - Wave Channel
  35. - Channel DAC
  36. - Trigger Event
  37. - Mixer
  38. - Power Control
  39. - Register Reading
  40. - Vin Mixing
  41. - Obscure Behavior
  42. - Differences
  43. - To Do
  44. - Thanks
  45.  
  46.  
  47. Overview
  48. --------
  49. The Game Boy has four sound channels: two square waves with adjustable
  50. duty, a programmable wave table, and a noise generator. Each has some
  51. kind of frequency (pitch) control. The first square channel also has an
  52. automatic frequency sweep unit to help with sound effects. The squares
  53. and noise each have a volume envelope unit to help with fading notes and
  54. sound effects, while the wave channel has only limited manual volume
  55. control. Each channel has a length counter that can silence the channel
  56. after a preset time, to handle note durations. Each channel can be
  57. individually panned to the far left, center, or far right. The master
  58. volume of the left and right outputs can also be adjusted.
  59.  
  60. Different versions of the Game Boy sound hardware have slightly
  61. different behavior. The following models have been tested:
  62.  
  63. DMG-CPU-03 original Game Boy
  64. DMG-CPU-05
  65. DMG-CPU-06
  66. MGB-LCPU-01 Game Boy Pocket
  67. CGB-CPU-02 Game Boy Color
  68. CGB-CPU-04
  69. CGB-CPU-05
  70.  
  71.  
  72. Registers
  73. ---------
  74. Sound registers are mapped to $FF10-$FF3F in memory. Each channel has
  75. five logical registers, NRx0-NRx4, though some don't use NRx0. The value
  76. written to bits marked with '-' has no effect. Reference to the value in
  77. a register means the last value written to it.
  78.  
  79. Name Addr 7654 3210 Function
  80. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  81. Square 1
  82. NR10 FF10 -PPP NSSS Sweep period, negate, shift
  83. NR11 FF11 DDLL LLLL Duty, Length load (64-L)
  84. NR12 FF12 VVVV APPP Starting volume, Envelope add mode, period
  85. NR13 FF13 FFFF FFFF Frequency LSB
  86. NR14 FF14 TL-- -FFF Trigger, Length enable, Frequency MSB
  87.  
  88. Square 2
  89. FF15 ---- ---- Not used
  90. NR21 FF16 DDLL LLLL Duty, Length load (64-L)
  91. NR22 FF17 VVVV APPP Starting volume, Envelope add mode, period
  92. NR23 FF18 FFFF FFFF Frequency LSB
  93. NR24 FF19 TL-- -FFF Trigger, Length enable, Frequency MSB
  94.  
  95. Wave
  96. NR30 FF1A E--- ---- DAC power
  97. NR31 FF1B LLLL LLLL Length load (256-L)
  98. NR32 FF1C -VV- ---- Volume code (00=0%, 01=100%, 10=50%, 11=25%)
  99. NR33 FF1D FFFF FFFF Frequency LSB
  100. NR34 FF1E TL-- -FFF Trigger, Length enable, Frequency MSB
  101.  
  102. Noise
  103. FF1F ---- ---- Not used
  104. NR41 FF20 --LL LLLL Length load (64-L)
  105. NR42 FF21 VVVV APPP Starting volume, Envelope add mode, period
  106. NR43 FF22 SSSS WDDD Clock shift, Width mode of LFSR, Divisor code
  107. NR44 FF23 TL-- ---- Trigger, Length enable
  108.  
  109. Control/Status
  110. NR50 FF24 ALLL BRRR Vin L enable, Left vol, Vin R enable, Right
  111. vol
  112. NR51 FF25 NW21 NW21 Left enables, Right enables
  113. NR52 FF26 P--- NW21 Power control/status, Channel length statuses
  114.  
  115. Not used
  116. FF27 ---- ----
  117. .... ---- ----
  118. FF2F ---- ----
  119.  
  120. Wave Table
  121. FF30 0000 1111 Samples 0 and 1
  122. ....
  123. FF3F 0000 1111 Samples 30 and 31
  124.  
  125.  
  126. Channels
  127. --------
  128. Each channel has a frequency timer which clocks a waveform generator.
  129. The waveform's volume is adjusted and fed to the mixer. The mixer
  130. converts each channel's waveform into an electrical signal and outputs
  131. this to the left and/or right channels. Finally, a master volume control
  132. adjusts the left and right outputs. The channels have the following
  133. units that are connected from left to right:
  134.  
  135. Square 1: Sweep -> Timer -> Duty -> Length Counter -> Envelope -> Mixer
  136.  
  137. Square 2: Timer -> Duty -> Length Counter -> Envelope -> Mixer
  138.  
  139. Wave: Timer -> Wave -> Length Counter -> Volume -> Mixer
  140.  
  141. Noise: Timer -> LFSR -> Length Counter -> Envelope -> Mixer
  142.  
  143. The mixer has a separate DAC for each channel, followed by on/off
  144. controls for left and right outputs. The left/right outputs from each
  145. channel are then added together and fed to the left/right master volume
  146. controls.
  147.  
  148. In general, all units in the channels are always running. For example,
  149. even if a channel is silent, several units will still be calculating
  150. values even though they aren't used.
  151.  
  152.  
  153. Timer
  154. -----
  155. A timer generates an output clock every N input clocks, where N is the
  156. timer's period. If a timer's rate is given as a frequency, its period is
  157. 4194304/frequency in Hz. Each timer has an internal counter that is
  158. decremented on each input clock. When the counter becomes zero, it is
  159. reloaded with the period and an output clock is generated.
  160.  
  161.  
  162. Frame Sequencer
  163. ---------------
  164. The frame sequencer generates low frequency clocks for the modulation
  165. units. It is clocked by a 512 Hz timer.
  166.  
  167. Step Length Ctr Vol Env Sweep
  168. - - - - - - - - - - - - - - - - - - - -
  169. 0 Clock - -
  170. 1 - - -
  171. 2 Clock - Clock
  172. 3 - - -
  173. 4 Clock - -
  174. 5 - - -
  175. 6 Clock - Clock
  176. 7 - Clock -
  177. - - - - - - - - - - - - - - - - - - - -
  178. Rate 256 Hz 64 Hz 128 Hz
  179.  
  180.  
  181. Length Counter
  182. --------------
  183. A length counter disables a channel when it decrements to zero. It
  184. contains an internal counter and enabled flag. Writing a byte to NRx1
  185. loads the counter with 64-data (256-data for wave channel). The counter
  186. can be reloaded at any time.
  187.  
  188. A channel is said to be disabled when the internal enabled flag is
  189. clear. When a channel is disabled, its volume unit receives 0, otherwise
  190. its volume unit receives the output of the waveform generator. Other
  191. units besides the length counter can enable/disable the channel as well.
  192.  
  193. Each length counter is clocked at 256 Hz by the frame sequencer. When
  194. clocked while enabled by NRx4 and the counter is not zero, it is
  195. decremented. If it becomes zero, the channel is disabled.
  196.  
  197.  
  198. Volume Envelope
  199. ---------------
  200. A volume envelope has a volume counter and an internal timer clocked at
  201. 64 Hz by the frame sequencer. When the timer generates a clock and the
  202. envelope period is not zero, a new volume is calculated by adding or
  203. subtracting (as set by NRx2) one from the current volume. If this new
  204. volume within the 0 to 15 range, the volume is updated, otherwise it is
  205. left unchanged and no further automatic increments/decrements are made
  206. to the volume until the channel is triggered again.
  207.  
  208. When the waveform input is zero the envelope outputs zero, otherwise it
  209. outputs the current volume.
  210.  
  211. Writing to NRx2 causes obscure effects on the volume that differ on
  212. different Game Boy models (see obscure behavior).
  213.  
  214.  
  215. Square Wave
  216. -----------
  217. A square channel's frequency timer period is set to (2048-frequency)*4.
  218. Four duty cycles are available, each waveform taking 8 frequency timer
  219. clocks to cycle through:
  220.  
  221. Duty Waveform Ratio
  222. - - - - - - - - - - - - -
  223. 0 00000001 12.5%
  224. 1 10000001 25%
  225. 2 10000111 50%
  226. 3 01111110 75%
  227.  
  228.  
  229. Frequency Sweep
  230. ---------------
  231. The first square channel has a frequency sweep unit, controlled by NR10.
  232. This has a timer, internal enabled flag, and frequency shadow register.
  233. It can periodically adjust square 1's frequency up or down.
  234.  
  235. During a trigger event, several things occur:
  236. - Square 1's frequency is copied to the shadow register.
  237. - The sweep timer is reloaded.
  238. - The internal enabled flag is set if either the sweep period or shift
  239. are non-zero, cleared otherwise.
  240. - If the sweep shift is non-zero, frequency calculation and the overflow
  241. check are performed immediately.
  242.  
  243. Frequency calculation consists of taking the value in the frequency
  244. shadow register, shifting it right by sweep shift, optionally negating
  245. the value, and summing this with the frequency shadow register to
  246. produce a new frequency. What is done with this new frequency depends on
  247. the context.
  248.  
  249. The overflow check simply calculates the new frequency and if this is
  250. greater than 2047, square 1 is disabled.
  251.  
  252. The sweep timer is clocked at 128 Hz by the frame sequencer. When it
  253. generates a clock and the sweep's internal enabled flag is set and the
  254. sweep period is not zero, a new frequency is calculated and the overflow
  255. check is performed. If the new frequency is 2047 or less and the sweep
  256. shift is not zero, this new frequency is written back to the shadow
  257. frequency and square 1's frequency in NR13 and NR14, then frequency
  258. calculation and overflow check are run AGAIN immediately using this new
  259. value, but this second new frequency is not written back.
  260.  
  261. Square 1's frequency can be modified via NR13 and NR14 while sweep is
  262. active, but the shadow frequency won't be affected so the next time the
  263. sweep updates the channel's frequency this modification will be lost.
  264.  
  265.  
  266. Noise Channel
  267. -------------
  268. The noise channel's frequency timer period is set by a base divisor
  269. shifted left some number of bits.
  270.  
  271. Divisor code Divisor
  272. - - - - - - - - - - - -
  273. 0 8
  274. 1 16
  275. 2 32
  276. 3 48
  277. 4 64
  278. 5 80
  279. 6 96
  280. 7 112
  281.  
  282. The linear feedback shift register (LFSR) generates a pseudo-random bit
  283. sequence. It has a 15-bit shift register with feedback. When clocked by
  284. the frequency timer, the low two bits (0 and 1) are XORed, all bits are
  285. shifted right by one, and the result of the XOR is put into the
  286. now-empty high bit. If width mode is 1 (NR43), the XOR result is ALSO
  287. put into bit 6 AFTER the shift, resulting in a 7-bit LFSR. The waveform
  288. output is bit 0 of the LFSR, INVERTED.
  289.  
  290.  
  291. Wave Channel
  292. ------------
  293. The wave channel plays a 32-entry wave table made up of 4-bit samples.
  294. Each byte encodes two samples, the first in the high bits. The wave
  295. channel has a sample buffer and position counter.
  296.  
  297. The wave channel's frequency timer period is set to (2048-frequency)*2.
  298. When the timer generates a clock, the position counter is advanced one
  299. sample in the wave table, looping back to the beginning when it goes
  300. past the end, then a sample is read into the sample buffer from this NEW
  301. position.
  302.  
  303. The DAC receives the current value from the upper/lower nybble of the
  304. sample buffer, shifted right by the volume control.
  305.  
  306. Code Shift Volume
  307. - - - - - - - - - - - -
  308. 0 4 0% (silent)
  309. 1 0 100%
  310. 2 1 50%
  311. 3 2 25%
  312.  
  313. Wave RAM can only be properly accessed when the channel is disabled (see
  314. obscure behavior).
  315.  
  316.  
  317. Trigger Event
  318. -------------
  319. Writing a value to NRx4 with bit 7 set causes the following things to
  320. occur:
  321.  
  322. - Channel is enabled (see length counter).
  323. - If length counter is zero, it is set to 64 (256 for wave channel).
  324. - Frequency timer is reloaded with period.
  325. - Volume envelope timer is reloaded with period.
  326. - Channel volume is reloaded from NRx2.
  327. - Noise channel's LFSR bits are all set to 1.
  328. - Wave channel's position is set to 0 but sample buffer is NOT refilled.
  329. - Square 1's sweep does several things (see frequency sweep).
  330.  
  331. Note that if the channel's DAC is off, after the above actions occur the
  332. channel will be immediately disabled again.
  333.  
  334.  
  335. Channel DAC
  336. -----------
  337. Each channel has a 4-bit digital-to-analog convertor (DAC). This
  338. converts the input value to a proportional output voltage. An input of 0
  339. generates -1.0 and an input of 15 generates +1.0, using arbitrary
  340. voltage units.
  341.  
  342. DAC power is controlled by the upper 5 bits of NRx2 (top bit of NR30 for
  343. wave channel). If these bits are not all clear, the DAC is on, otherwise
  344. it's off and outputs 0 volts. Also, any time the DAC is off the channel
  345. is kept disabled (but turning the DAC back on does NOT enable the
  346. channel).
  347.  
  348.  
  349. Mixer
  350. -----
  351. Each channel's DAC output goes to a pair of on/off switches for the left
  352. and right channels before they are sent to the left/right mixers. A
  353. mixer simply adds the voltages from each channel together. These
  354. left/right switches are controlled by NR51. When a switch is off, the
  355. mixer receives 0 volts.
  356.  
  357. The Vin bits of NR50 control mixing of the Vin signal from the
  358. cartridge, allowing extra sound hardware.
  359.  
  360. The mixed left/right signals go to the left/right master volume
  361. controls. These multiply the signal by (volume+1). The volume step
  362. relative to the channel DAC is such that a single channel enabled via
  363. NR51 playing at volume of 2 with a master volume of 7 is about as loud
  364. as that channel playing at volume 15 with a master volume of 0.
  365.  
  366.  
  367. Power Control
  368. -------------
  369. NR52 controls power to the sound hardware. When powered off, all
  370. registers (NR10-NR51) are instantly written with zero and any writes to
  371. those registers are ignored while power remains off (except on the DMG,
  372. where length counters are unaffected by power and can still be written
  373. while off). When powered on, the frame sequencer is reset so that the
  374. next step will be 0, the square duty units are reset to the first step
  375. of the waveform, and the wave channel's sample buffer is reset to 0.
  376.  
  377. Power state does not affect wave memory, which can always be
  378. read/written. It also does not affect the 512 Hz timer that feeds the
  379. frame sequencer.
  380.  
  381. When the Game Boy is switched on (before the internal boot ROM
  382. executes), the values in the wave table depend on the model. On the DMG,
  383. they are somewhat random, though the particular pattern is generally the
  384. same for each individual Game Boy unit. The game R-Type doesn't
  385. initialize wave RAM and thus relies on these. One set of values is
  386.  
  387. 84 40 43 AA 2D 78 92 3C 60 59 59 B0 34 B8 2E DA
  388.  
  389. On the Game Boy Color, the values are consistently
  390.  
  391. 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF
  392.  
  393.  
  394. Register Reading
  395. ----------------
  396. Reading NR52 yields the current power status and each channel's enabled
  397. status (from the length counter).
  398.  
  399. Wave RAM reads back as the last value written.
  400.  
  401. When an NRxx register is read back, the last written value ORed with the
  402. following is returned:
  403.  
  404. NRx0 NRx1 NRx2 NRx3 NRx4
  405. - - - - - - - - - - - - - -
  406. NR1x $80 $3F $00 $FF $BF
  407. NR2x $FF $3F $00 $FF $BF
  408. NR3x $7F $FF $9F $FF $BF
  409. NR4x $FF $FF $00 $00 $BF
  410. NR5x $00 $00 $70
  411.  
  412. $FF27-$FF2F always read back as $FF
  413.  
  414. That is, the channel length counters, frequencies, and unused bits
  415. always read back as set to all 1s.
  416.  
  417.  
  418. Vin Mixing
  419. ----------
  420. The cartridge connector includes a sound input called Vin. When enabled
  421. via NR50, it is mixed in before the master volume controls. On the DMG
  422. and MGB, 0.847 volts gives equivalent to 0 on a channel DAC, and 3.710
  423. volts is equivalent to 15 on a DAC, with other values linearly
  424. distributed between those voltages. On the CGB, the range is 1.920 volts
  425. to 2.740 volts, a quarter of the DMG range, thus sound fed to the CGB's
  426. Vin is significantly louder.
  427.  
  428.  
  429. Obscure Behavior
  430. ----------------
  431. - The volume envelope and sweep timers treat a period of 0 as 8.
  432.  
  433. - Just after powering on, the first duty step of the square waves after
  434. they are triggered for the first time is played as if it were 0. Also,
  435. the square duty sequence clocking is disabled until the first trigger.
  436.  
  437. - When triggering the wave channel, the first sample to play is the
  438. previous one still in the high nybble of the sample buffer, and the next
  439. sample is the second nybble from the wave table. This is because it
  440. doesn't load the first byte on trigger like it "should". The first
  441. nybble from the wave table is thus not played until the waveform loops.
  442.  
  443. - When triggering a square channel, the low two bits of the frequency
  444. timer are NOT modified.
  445.  
  446. - Extra length clocking occurs when writing to NRx4 when the frame
  447. sequencer's next step is one that doesn't clock the length counter. In
  448. this case, if the length counter was PREVIOUSLY disabled and now enabled
  449. and the length counter is not zero, it is decremented. If this decrement
  450. makes it zero and trigger is clear, the channel is disabled. On the
  451. CGB-02, the length counter only has to have been disabled before; the
  452. current length enable state doesn't matter. This breaks at least one
  453. game (Prehistorik Man), and was fixed on CGB-04 and CGB-05.
  454.  
  455. - If a channel is triggered when the frame sequencer's next step is one
  456. that doesn't clock the length counter and the length counter is now
  457. enabled and length is being set to 64 (256 for wave channel) because it
  458. was previously zero, it is set to 63 instead (255 for wave channel).
  459.  
  460. - If a channel is triggered when the frame sequencer's next step will
  461. clock the volume envelope, the envelope's timer is reloaded with one
  462. greater than it would have been.
  463.  
  464. - Using a noise channel clock shift of 14 or 15 results in the LFSR
  465. receiving no clocks.
  466.  
  467. - Clearing the sweep negate mode bit in NR10 after at least one sweep
  468. calculation has been made using the negate mode since the last trigger
  469. causes the channel to be immediately disabled. This prevents you from
  470. having the sweep lower the frequency then raise the frequency without a
  471. trigger inbetween.
  472.  
  473. - If the wave channel is enabled, accessing any byte from $FF30-$FF3F is
  474. equivalent to accessing the current byte selected by the waveform
  475. position. Further, on the DMG accesses will only work in this manner if
  476. made within a couple of clocks of the wave channel accessing wave RAM;
  477. if made at any other time, reads return $FF and writes have no effect.
  478.  
  479. - Triggering the wave channel on the DMG while it reads a sample byte
  480. will alter the first four bytes of wave RAM. If the channel was reading
  481. one of the first four bytes, only the first byte will be rewritten with
  482. the byte being read. If the channel was reading one of the later 12
  483. bytes, the first FOUR bytes of wave RAM will be rewritten with the four
  484. aligned bytes that the read was from (bytes 4-7, 8-11, or 12-15); for
  485. example if it were reading byte 9 when it was retriggered, the first
  486. four bytes would be rewritten with the contents of bytes 8-11. To avoid
  487. this corruption you should stop the wave by writing 0 then $80 to NR30
  488. before triggering it again. The game Duck Tales encounters this issue
  489. part way through most songs.
  490.  
  491. - "Zombie" mode: the volume can be manually altered while a channel is
  492. playing by writing to NRx2. Behavior depends on the old and new values
  493. of NRx2, and whether the envlope has stopped automatic updates. The
  494. CGB-02 and CGB-04 are the most consistent:
  495.  
  496. - If the old envelope period was zero and the envelope is still
  497. doing automatic updates, volume is incremented by 1, otherwise if the
  498. envelope was in subtract mode, volume is incremented by 2.
  499. - If the mode was changed (add to subtract or subtract to add),
  500. volume is set to 16-volume.
  501. - Only the low 4 bits of volume are kept after the above operations.
  502.  
  503. Other models behave differently, especially the DMG units which have
  504. crazy behavior in some cases. The only useful consistent behavior is
  505. using add mode with a period of zero in order to increment the volume by
  506. 1. That is, write $V8 to NRx2 to set the initial volume to V before
  507. triggering the channel, then write $08 to NRx2 to increment the volume
  508. as the sound plays (repeat 15 times to decrement the volume by 1). This
  509. allows manual volume control on all units tested.
  510.  
  511. - When all four channel DACs are off, the master volume units are
  512. disconnected from the sound output and the output level becomes 0. When
  513. any channel DAC is on, a high-pass filter capacitor is connected which
  514. slowly removes any DC component from the signal. The following code
  515. applied at 4194304 Hz implements these two behaviors for one of the DMG
  516. output channels (unoptimized floating point for clarity):
  517.  
  518. static double capacitor = 0.0;
  519.  
  520. double high_pass( double in, bool dacs_enabled )
  521. {
  522. double out = 0.0;
  523. if ( dacs_enabled )
  524. {
  525. out = in - capacitor;
  526.  
  527. // capacitor slowly charges to 'in' via their difference
  528. capacitor = in - out * 0.999958; // use 0.998943 for MGB&CGB
  529. }
  530. return out;
  531. }
  532.  
  533. The charge factor can be calculated for any output sampling rate as
  534. 0.999958^(4194304/rate). So if you were applying high_pass() at 44100
  535. Hz, you'd use a charge factor of 0.996.
  536.  
  537.  
  538. Differences
  539. -----------
  540. This summarizes differences I've found among the models tested.
  541.  
  542. Wave RAM access:
  543. - Possible only when it's doing wave RAM read (DMG-03, DMG-05, DMG-06,
  544. MGB-01).
  545. - Can be accessed any time (CGB-02, CGB-04, CGB-05).
  546.  
  547. Wave channel re-trigger without disabling first (via NR30):
  548. - Re-writes first four bytes of wave RAM (DMG-03, DMG-05, DMG-06,
  549. MGB-01).
  550. - Behaves normally (CGB-02, CGB-04, CGB-05).
  551.  
  552. Length counters and power off:
  553. - Preserved and can be written while off (DMG-03, DMG-05, DMG-06,
  554. MGB-01).
  555. - Always zero at power on (CGB-02, CGB-04, CGB-05).
  556.  
  557. Length clocking on NRx4:
  558. - New length enable doesn't matter (CGB-02).
  559. - Length must now be enabled (DMG-03, DMG-05, DMG-06, CGB-04, CGB-05,
  560. MGB-01).
  561.  
  562. Volume changes on NRx2 write:
  563. - $x0 to $xx and $x7 to $xx are very screwey (DMG-03, DMG-05, DMG-06,
  564. MGB-01).
  565. - Behavior as described in obscure behavior (CGB-02, CGB-04).
  566. - If mode isn't being changed, only $x8 to $xx affects volume. Mode
  567. change is also a bit different (CGB-05).
  568.  
  569.  
  570. To Do
  571. -----
  572. - Using an envelope or sweep period of 0 then switching to another
  573. period also causes an extra clock in some cases.
  574.  
  575. - Frequency sweep has some really intricate behavior when rewriting
  576. sweep register
  577.  
  578. - Noise's frequency timer is more complex than described, resulting in
  579. trigger doing something more than simply reloading it. It may have
  580. multiple dividers to achieve the documented periods, with only some of
  581. them being reset on trigger.
  582.  
  583. - Behavior when triggering and writing to registers within a few clocks
  584. of frame sequencer events has yet to be determined. There will be lots
  585. of odd things uncovered for sure.
  586.  
  587. - Figure out exactly how noise LFSR is implemented with regard to mode
  588. changes.
  589.  
  590. - Document exact timing for DMG wave issues.
  591.  
  592.  
  593. Thanks
  594. ------
  595. - Lord Nightmare for GBSOUND.txt, assistance, testing, GBs to test.
  596. - Laguna for the gnuboy emulator.
  597. - Ville Helin for WLA DX GB-Z80 assembler.
  598. - sinamas for feedback about this document and my test ROMs.
  599.  
  600. --
  601. Shay Green <gblargg@gmail.com>
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