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gameboy sound emulation by blargg

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Jun 21st, 2012
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  1. Game Boy Sound Operation
  2. ------------------------
  3. Shay Green (blargg)
  4. http://www.slack.net/~ant/
  5.  
  6. ** This is an incomplete draft
  7.  
  8. This documents the behavior of Game Boy sound; details which aren't
  9. relevant to the observable behavior have been omitted unless they
  10. clarify understanding. It is aimed at answering all questions about
  11. exact operation, rather than describing how to use sound effectively in
  12. Game Boy programs. Values in hexadecimal (base 16) are generally written
  13. with a $ prefix. Bits are numbered from 0 to 7, where bit N has a weight
  14. of 2^N. A nybble is 4 bits, half a byte. Obscure behavior is described
  15. separately to increase clarity elsewhere.
  16.  
  17. Contact me for a set of test ROMs that verify most behavior described
  18. here.
  19.  
  20.  
  21. Contents
  22. --------
  23. - Overview
  24. - Registers
  25. - Channels
  26. - Timer
  27. - Frame Sequencer
  28. - Length Counter
  29. - Volume Envelope
  30. - Square Wave
  31. - Frequency Sweep
  32. - Noise Channel
  33. - Wave Channel
  34. - Channel DAC
  35. - Trigger Event
  36. - Mixer
  37. - Power Control
  38. - Register Reading
  39. - Vin Mixing
  40. - Obscure Behavior
  41. - Differences
  42. - To Do
  43. - Thanks
  44.  
  45.  
  46. Overview
  47. --------
  48. The Game Boy has four sound channels: two square waves with adjustable
  49. duty, a programmable wave table, and a noise generator. Each has some
  50. kind of frequency (pitch) control. The first square channel also has an
  51. automatic frequency sweep unit to help with sound effects. The squares
  52. and noise each have a volume envelope unit to help with fading notes and
  53. sound effects, while the wave channel has only limited manual volume
  54. control. Each channel has a length counter that can silence the channel
  55. after a preset time, to handle note durations. Each channel can be
  56. individually panned to the far left, center, or far right. The master
  57. volume of the left and right outputs can also be adjusted.
  58.  
  59. Different versions of the Game Boy sound hardware have slightly
  60. different behavior. The following models have been tested:
  61.  
  62. DMG-CPU-03 original Game Boy
  63. DMG-CPU-05
  64. DMG-CPU-06
  65. MGB-LCPU-01 Game Boy Pocket
  66. CGB-CPU-02 Game Boy Color
  67. CGB-CPU-04
  68. CGB-CPU-05
  69.  
  70.  
  71. Registers
  72. ---------
  73. Sound registers are mapped to $FF10-$FF3F in memory. Each channel has
  74. five logical registers, NRx0-NRx4, though some don't use NRx0. The value
  75. written to bits marked with '-' has no effect. Reference to the value in
  76. a register means the last value written to it.
  77.  
  78. Name Addr 7654 3210 Function
  79. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  80. Square 1
  81. NR10 FF10 -PPP NSSS Sweep period, negate, shift
  82. NR11 FF11 DDLL LLLL Duty, Length load (64-L)
  83. NR12 FF12 VVVV APPP Starting volume, Envelope add mode, period
  84. NR13 FF13 FFFF FFFF Frequency LSB
  85. NR14 FF14 TL-- -FFF Trigger, Length enable, Frequency MSB
  86.  
  87. Square 2
  88. FF15 ---- ---- Not used
  89. NR21 FF16 DDLL LLLL Duty, Length load (64-L)
  90. NR22 FF17 VVVV APPP Starting volume, Envelope add mode, period
  91. NR23 FF18 FFFF FFFF Frequency LSB
  92. NR24 FF19 TL-- -FFF Trigger, Length enable, Frequency MSB
  93.  
  94. Wave
  95. NR30 FF1A E--- ---- DAC power
  96. NR31 FF1B LLLL LLLL Length load (256-L)
  97. NR32 FF1C -VV- ---- Volume code (00=0%, 01=100%, 10=50%, 11=25%)
  98. NR33 FF1D FFFF FFFF Frequency LSB
  99. NR34 FF1E TL-- -FFF Trigger, Length enable, Frequency MSB
  100.  
  101. Noise
  102. FF1F ---- ---- Not used
  103. NR41 FF20 --LL LLLL Length load (64-L)
  104. NR42 FF21 VVVV APPP Starting volume, Envelope add mode, period
  105. NR43 FF22 SSSS WDDD Clock shift, Width mode of LFSR, Divisor code
  106. NR44 FF23 TL-- ---- Trigger, Length enable
  107.  
  108. Control/Status
  109. NR50 FF24 ALLL BRRR Vin L enable, Left vol, Vin R enable, Right
  110. vol
  111. NR51 FF25 NW21 NW21 Left enables, Right enables
  112. NR52 FF26 P--- NW21 Power control/status, Channel length statuses
  113.  
  114. Not used
  115. FF27 ---- ----
  116. .... ---- ----
  117. FF2F ---- ----
  118.  
  119. Wave Table
  120. FF30 0000 1111 Samples 0 and 1
  121. ....
  122. FF3F 0000 1111 Samples 30 and 31
  123.  
  124.  
  125. Channels
  126. --------
  127. Each channel has a frequency timer which clocks a waveform generator.
  128. The waveform's volume is adjusted and fed to the mixer. The mixer
  129. converts each channel's waveform into an electrical signal and outputs
  130. this to the left and/or right channels. Finally, a master volume control
  131. adjusts the left and right outputs. The channels have the following
  132. units that are connected from left to right:
  133.  
  134. Square 1: Sweep -> Timer -> Duty -> Length Counter -> Envelope -> Mixer
  135.  
  136. Square 2: Timer -> Duty -> Length Counter -> Envelope -> Mixer
  137.  
  138. Wave: Timer -> Wave -> Length Counter -> Volume -> Mixer
  139.  
  140. Noise: Timer -> LFSR -> Length Counter -> Envelope -> Mixer
  141.  
  142. The mixer has a separate DAC for each channel, followed by on/off
  143. controls for left and right outputs. The left/right outputs from each
  144. channel are then added together and fed to the left/right master volume
  145. controls.
  146.  
  147. In general, all units in the channels are always running. For example,
  148. even if a channel is silent, several units will still be calculating
  149. values even though they aren't used.
  150.  
  151.  
  152. Timer
  153. -----
  154. A timer generates an output clock every N input clocks, where N is the
  155. timer's period. If a timer's rate is given as a frequency, its period is
  156. 4194304/frequency in Hz. Each timer has an internal counter that is
  157. decremented on each input clock. When the counter becomes zero, it is
  158. reloaded with the period and an output clock is generated.
  159.  
  160.  
  161. Frame Sequencer
  162. ---------------
  163. The frame sequencer generates low frequency clocks for the modulation
  164. units. It is clocked by a 512 Hz timer.
  165.  
  166. Step Length Ctr Vol Env Sweep
  167. - - - - - - - - - - - - - - - - - - - -
  168. 0 Clock - -
  169. 1 - - -
  170. 2 Clock - Clock
  171. 3 - - -
  172. 4 Clock - -
  173. 5 - - -
  174. 6 Clock - Clock
  175. 7 - Clock -
  176. - - - - - - - - - - - - - - - - - - - -
  177. Rate 256 Hz 64 Hz 128 Hz
  178.  
  179.  
  180. Length Counter
  181. --------------
  182. A length counter disables a channel when it decrements to zero. It
  183. contains an internal counter and enabled flag. Writing a byte to NRx1
  184. loads the counter with 64-data (256-data for wave channel). The counter
  185. can be reloaded at any time.
  186.  
  187. A channel is said to be disabled when the internal enabled flag is
  188. clear. When a channel is disabled, its volume unit receives 0, otherwise
  189. its volume unit receives the output of the waveform generator. Other
  190. units besides the length counter can enable/disable the channel as well.
  191.  
  192. Each length counter is clocked at 256 Hz by the frame sequencer. When
  193. clocked while enabled by NRx4 and the counter is not zero, it is
  194. decremented. If it becomes zero, the channel is disabled.
  195.  
  196.  
  197. Volume Envelope
  198. ---------------
  199. A volume envelope has a volume counter and an internal timer clocked at
  200. 64 Hz by the frame sequencer. When the timer generates a clock and the
  201. envelope period is not zero, a new volume is calculated by adding or
  202. subtracting (as set by NRx2) one from the current volume. If this new
  203. volume within the 0 to 15 range, the volume is updated, otherwise it is
  204. left unchanged and no further automatic increments/decrements are made
  205. to the volume until the channel is triggered again.
  206.  
  207. When the waveform input is zero the envelope outputs zero, otherwise it
  208. outputs the current volume.
  209.  
  210. Writing to NRx2 causes obscure effects on the volume that differ on
  211. different Game Boy models (see obscure behavior).
  212.  
  213.  
  214. Square Wave
  215. -----------
  216. A square channel's frequency timer period is set to (2048-frequency)*4.
  217. Four duty cycles are available, each waveform taking 8 frequency timer
  218. clocks to cycle through:
  219.  
  220. Duty Waveform Ratio
  221. - - - - - - - - - - - - -
  222. 0 00000001 12.5%
  223. 1 10000001 25%
  224. 2 10000111 50%
  225. 3 01111110 75%
  226.  
  227.  
  228. Frequency Sweep
  229. ---------------
  230. The first square channel has a frequency sweep unit, controlled by NR10.
  231. This has a timer, internal enabled flag, and frequency shadow register.
  232. It can periodically adjust square 1's frequency up or down.
  233.  
  234. During a trigger event, several things occur:
  235. - Square 1's frequency is copied to the shadow register.
  236. - The sweep timer is reloaded.
  237. - The internal enabled flag is set if either the sweep period or shift
  238. are non-zero, cleared otherwise.
  239. - If the sweep shift is non-zero, frequency calculation and the overflow
  240. check are performed immediately.
  241.  
  242. Frequency calculation consists of taking the value in the frequency
  243. shadow register, shifting it right by sweep shift, optionally negating
  244. the value, and summing this with the frequency shadow register to
  245. produce a new frequency. What is done with this new frequency depends on
  246. the context.
  247.  
  248. The overflow check simply calculates the new frequency and if this is
  249. greater than 2047, square 1 is disabled.
  250.  
  251. The sweep timer is clocked at 128 Hz by the frame sequencer. When it
  252. generates a clock and the sweep's internal enabled flag is set and the
  253. sweep period is not zero, a new frequency is calculated and the overflow
  254. check is performed. If the new frequency is 2047 or less and the sweep
  255. shift is not zero, this new frequency is written back to the shadow
  256. frequency and square 1's frequency in NR13 and NR14, then frequency
  257. calculation and overflow check are run AGAIN immediately using this new
  258. value, but this second new frequency is not written back.
  259.  
  260. Square 1's frequency can be modified via NR13 and NR14 while sweep is
  261. active, but the shadow frequency won't be affected so the next time the
  262. sweep updates the channel's frequency this modification will be lost.
  263.  
  264.  
  265. Noise Channel
  266. -------------
  267. The noise channel's frequency timer period is set by a base divisor
  268. shifted left some number of bits.
  269.  
  270. Divisor code Divisor
  271. - - - - - - - - - - - -
  272. 0 8
  273. 1 16
  274. 2 32
  275. 3 48
  276. 4 64
  277. 5 80
  278. 6 96
  279. 7 112
  280.  
  281. The linear feedback shift register (LFSR) generates a pseudo-random bit
  282. sequence. It has a 15-bit shift register with feedback. When clocked by
  283. the frequency timer, the low two bits (0 and 1) are XORed, all bits are
  284. shifted right by one, and the result of the XOR is put into the
  285. now-empty high bit. If width mode is 1 (NR43), the XOR result is ALSO
  286. put into bit 6 AFTER the shift, resulting in a 7-bit LFSR. The waveform
  287. output is bit 0 of the LFSR, INVERTED.
  288.  
  289.  
  290. Wave Channel
  291. ------------
  292. The wave channel plays a 32-entry wave table made up of 4-bit samples.
  293. Each byte encodes two samples, the first in the high bits. The wave
  294. channel has a sample buffer and position counter.
  295.  
  296. The wave channel's frequency timer period is set to (2048-frequency)*2.
  297. When the timer generates a clock, the position counter is advanced one
  298. sample in the wave table, looping back to the beginning when it goes
  299. past the end, then a sample is read into the sample buffer from this NEW
  300. position.
  301.  
  302. The DAC receives the current value from the upper/lower nybble of the
  303. sample buffer, shifted right by the volume control.
  304.  
  305. Code Shift Volume
  306. - - - - - - - - - - - -
  307. 0 4 0% (silent)
  308. 1 0 100%
  309. 2 1 50%
  310. 3 2 25%
  311.  
  312. Wave RAM can only be properly accessed when the channel is disabled (see
  313. obscure behavior).
  314.  
  315.  
  316. Trigger Event
  317. -------------
  318. Writing a value to NRx4 with bit 7 set causes the following things to
  319. occur:
  320.  
  321. - Channel is enabled (see length counter).
  322. - If length counter is zero, it is set to 64 (256 for wave channel).
  323. - Frequency timer is reloaded with period.
  324. - Volume envelope timer is reloaded with period.
  325. - Channel volume is reloaded from NRx2.
  326. - Noise channel's LFSR bits are all set to 1.
  327. - Wave channel's position is set to 0 but sample buffer is NOT refilled.
  328. - Square 1's sweep does several things (see frequency sweep).
  329.  
  330. Note that if the channel's DAC is off, after the above actions occur the
  331. channel will be immediately disabled again.
  332.  
  333.  
  334. Channel DAC
  335. -----------
  336. Each channel has a 4-bit digital-to-analog convertor (DAC). This
  337. converts the input value to a proportional output voltage. An input of 0
  338. generates -1.0 and an input of 15 generates +1.0, using arbitrary
  339. voltage units.
  340.  
  341. DAC power is controlled by the upper 5 bits of NRx2 (top bit of NR30 for
  342. wave channel). If these bits are not all clear, the DAC is on, otherwise
  343. it's off and outputs 0 volts. Also, any time the DAC is off the channel
  344. is kept disabled (but turning the DAC back on does NOT enable the
  345. channel).
  346.  
  347.  
  348. Mixer
  349. -----
  350. Each channel's DAC output goes to a pair of on/off switches for the left
  351. and right channels before they are sent to the left/right mixers. A
  352. mixer simply adds the voltages from each channel together. These
  353. left/right switches are controlled by NR51. When a switch is off, the
  354. mixer receives 0 volts.
  355.  
  356. The Vin bits of NR50 control mixing of the Vin signal from the
  357. cartridge, allowing extra sound hardware.
  358.  
  359. The mixed left/right signals go to the left/right master volume
  360. controls. These multiply the signal by (volume+1). The volume step
  361. relative to the channel DAC is such that a single channel enabled via
  362. NR51 playing at volume of 2 with a master volume of 7 is about as loud
  363. as that channel playing at volume 15 with a master volume of 0.
  364.  
  365.  
  366. Power Control
  367. -------------
  368. NR52 controls power to the sound hardware. When powered off, all
  369. registers (NR10-NR51) are instantly written with zero and any writes to
  370. those registers are ignored while power remains off (except on the DMG,
  371. where length counters are unaffected by power and can still be written
  372. while off). When powered on, the frame sequencer is reset so that the
  373. next step will be 0, the square duty units are reset to the first step
  374. of the waveform, and the wave channel's sample buffer is reset to 0.
  375.  
  376. Power state does not affect wave memory, which can always be
  377. read/written. It also does not affect the 512 Hz timer that feeds the
  378. frame sequencer.
  379.  
  380. When the Game Boy is switched on (before the internal boot ROM
  381. executes), the values in the wave table depend on the model. On the DMG,
  382. they are somewhat random, though the particular pattern is generally the
  383. same for each individual Game Boy unit. The game R-Type doesn't
  384. initialize wave RAM and thus relies on these. One set of values is
  385.  
  386. 84 40 43 AA 2D 78 92 3C 60 59 59 B0 34 B8 2E DA
  387.  
  388. On the Game Boy Color, the values are consistently
  389.  
  390. 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF
  391.  
  392.  
  393. Register Reading
  394. ----------------
  395. Reading NR52 yields the current power status and each channel's enabled
  396. status (from the length counter).
  397.  
  398. Wave RAM reads back as the last value written.
  399.  
  400. When an NRxx register is read back, the last written value ORed with the
  401. following is returned:
  402.  
  403. NRx0 NRx1 NRx2 NRx3 NRx4
  404. - - - - - - - - - - - - - -
  405. NR1x $80 $3F $00 $FF $BF
  406. NR2x $FF $3F $00 $FF $BF
  407. NR3x $7F $FF $9F $FF $BF
  408. NR4x $FF $FF $00 $00 $BF
  409. NR5x $00 $00 $70
  410.  
  411. $FF27-$FF2F always read back as $FF
  412.  
  413. That is, the channel length counters, frequencies, and unused bits
  414. always read back as set to all 1s.
  415.  
  416.  
  417. Vin Mixing
  418. ----------
  419. The cartridge connector includes a sound input called Vin. When enabled
  420. via NR50, it is mixed in before the master volume controls. On the DMG
  421. and MGB, 0.847 volts gives equivalent to 0 on a channel DAC, and 3.710
  422. volts is equivalent to 15 on a DAC, with other values linearly
  423. distributed between those voltages. On the CGB, the range is 1.920 volts
  424. to 2.740 volts, a quarter of the DMG range, thus sound fed to the CGB's
  425. Vin is significantly louder.
  426.  
  427.  
  428. Obscure Behavior
  429. ----------------
  430. - The volume envelope and sweep timers treat a period of 0 as 8.
  431.  
  432. - Just after powering on, the first duty step of the square waves after
  433. they are triggered for the first time is played as if it were 0. Also,
  434. the square duty sequence clocking is disabled until the first trigger.
  435.  
  436. - When triggering the wave channel, the first sample to play is the
  437. previous one still in the high nybble of the sample buffer, and the next
  438. sample is the second nybble from the wave table. This is because it
  439. doesn't load the first byte on trigger like it "should". The first
  440. nybble from the wave table is thus not played until the waveform loops.
  441.  
  442. - When triggering a square channel, the low two bits of the frequency
  443. timer are NOT modified.
  444.  
  445. - Extra length clocking occurs when writing to NRx4 when the frame
  446. sequencer's next step is one that doesn't clock the length counter. In
  447. this case, if the length counter was PREVIOUSLY disabled and now enabled
  448. and the length counter is not zero, it is decremented. If this decrement
  449. makes it zero and trigger is clear, the channel is disabled. On the
  450. CGB-02, the length counter only has to have been disabled before; the
  451. current length enable state doesn't matter. This breaks at least one
  452. game (Prehistorik Man), and was fixed on CGB-04 and CGB-05.
  453.  
  454. - If a channel is triggered when the frame sequencer's next step is one
  455. that doesn't clock the length counter and the length counter is now
  456. enabled and length is being set to 64 (256 for wave channel) because it
  457. was previously zero, it is set to 63 instead (255 for wave channel).
  458.  
  459. - If a channel is triggered when the frame sequencer's next step will
  460. clock the volume envelope, the envelope's timer is reloaded with one
  461. greater than it would have been.
  462.  
  463. - Using a noise channel clock shift of 14 or 15 results in the LFSR
  464. receiving no clocks.
  465.  
  466. - Clearing the sweep negate mode bit in NR10 after at least one sweep
  467. calculation has been made using the negate mode since the last trigger
  468. causes the channel to be immediately disabled. This prevents you from
  469. having the sweep lower the frequency then raise the frequency without a
  470. trigger inbetween.
  471.  
  472. - If the wave channel is enabled, accessing any byte from $FF30-$FF3F is
  473. equivalent to accessing the current byte selected by the waveform
  474. position. Further, on the DMG accesses will only work in this manner if
  475. made within a couple of clocks of the wave channel accessing wave RAM;
  476. if made at any other time, reads return $FF and writes have no effect.
  477.  
  478. - Triggering the wave channel on the DMG while it reads a sample byte
  479. will alter the first four bytes of wave RAM. If the channel was reading
  480. one of the first four bytes, only the first byte will be rewritten with
  481. the byte being read. If the channel was reading one of the later 12
  482. bytes, the first FOUR bytes of wave RAM will be rewritten with the four
  483. aligned bytes that the read was from (bytes 4-7, 8-11, or 12-15); for
  484. example if it were reading byte 9 when it was retriggered, the first
  485. four bytes would be rewritten with the contents of bytes 8-11. To avoid
  486. this corruption you should stop the wave by writing 0 then $80 to NR30
  487. before triggering it again. The game Duck Tales encounters this issue
  488. part way through most songs.
  489.  
  490. - "Zombie" mode: the volume can be manually altered while a channel is
  491. playing by writing to NRx2. Behavior depends on the old and new values
  492. of NRx2, and whether the envlope has stopped automatic updates. The
  493. CGB-02 and CGB-04 are the most consistent:
  494.  
  495. - If the old envelope period was zero and the envelope is still
  496. doing automatic updates, volume is incremented by 1, otherwise if the
  497. envelope was in subtract mode, volume is incremented by 2.
  498. - If the mode was changed (add to subtract or subtract to add),
  499. volume is set to 16-volume.
  500. - Only the low 4 bits of volume are kept after the above operations.
  501.  
  502. Other models behave differently, especially the DMG units which have
  503. crazy behavior in some cases. The only useful consistent behavior is
  504. using add mode with a period of zero in order to increment the volume by
  505. 1. That is, write $V8 to NRx2 to set the initial volume to V before
  506. triggering the channel, then write $08 to NRx2 to increment the volume
  507. as the sound plays (repeat 15 times to decrement the volume by 1). This
  508. allows manual volume control on all units tested.
  509.  
  510. - When all four channel DACs are off, the master volume units are
  511. disconnected from the sound output and the output level becomes 0. When
  512. any channel DAC is on, a high-pass filter capacitor is connected which
  513. slowly removes any DC component from the signal. The following code
  514. applied at 4194304 Hz implements these two behaviors for one of the DMG
  515. output channels (unoptimized floating point for clarity):
  516.  
  517. static double capacitor = 0.0;
  518.  
  519. double high_pass( double in, bool dacs_enabled )
  520. {
  521. double out = 0.0;
  522. if ( dacs_enabled )
  523. {
  524. out = in - capacitor;
  525.  
  526. // capacitor slowly charges to 'in' via their difference
  527. capacitor = in - out * 0.999958; // use 0.998943 for MGB&CGB
  528. }
  529. return out;
  530. }
  531.  
  532. The charge factor can be calculated for any output sampling rate as
  533. 0.999958^(4194304/rate). So if you were applying high_pass() at 44100
  534. Hz, you'd use a charge factor of 0.996.
  535.  
  536.  
  537. Differences
  538. -----------
  539. This summarizes differences I've found among the models tested.
  540.  
  541. Wave RAM access:
  542. - Possible only when it's doing wave RAM read (DMG-03, DMG-05, DMG-06,
  543. MGB-01).
  544. - Can be accessed any time (CGB-02, CGB-04, CGB-05).
  545.  
  546. Wave channel re-trigger without disabling first (via NR30):
  547. - Re-writes first four bytes of wave RAM (DMG-03, DMG-05, DMG-06,
  548. MGB-01).
  549. - Behaves normally (CGB-02, CGB-04, CGB-05).
  550.  
  551. Length counters and power off:
  552. - Preserved and can be written while off (DMG-03, DMG-05, DMG-06,
  553. MGB-01).
  554. - Always zero at power on (CGB-02, CGB-04, CGB-05).
  555.  
  556. Length clocking on NRx4:
  557. - New length enable doesn't matter (CGB-02).
  558. - Length must now be enabled (DMG-03, DMG-05, DMG-06, CGB-04, CGB-05,
  559. MGB-01).
  560.  
  561. Volume changes on NRx2 write:
  562. - $x0 to $xx and $x7 to $xx are very screwey (DMG-03, DMG-05, DMG-06,
  563. MGB-01).
  564. - Behavior as described in obscure behavior (CGB-02, CGB-04).
  565. - If mode isn't being changed, only $x8 to $xx affects volume. Mode
  566. change is also a bit different (CGB-05).
  567.  
  568.  
  569. To Do
  570. -----
  571. - Using an envelope or sweep period of 0 then switching to another
  572. period also causes an extra clock in some cases.
  573.  
  574. - Frequency sweep has some really intricate behavior when rewriting
  575. sweep register
  576.  
  577. - Noise's frequency timer is more complex than described, resulting in
  578. trigger doing something more than simply reloading it. It may have
  579. multiple dividers to achieve the documented periods, with only some of
  580. them being reset on trigger.
  581.  
  582. - Behavior when triggering and writing to registers within a few clocks
  583. of frame sequencer events has yet to be determined. There will be lots
  584. of odd things uncovered for sure.
  585.  
  586. - Figure out exactly how noise LFSR is implemented with regard to mode
  587. changes.
  588.  
  589. - Document exact timing for DMG wave issues.
  590.  
  591.  
  592. Thanks
  593. ------
  594. - Lord Nightmare for GBSOUND.txt, assistance, testing, GBs to test.
  595. - Laguna for the gnuboy emulator.
  596. - Ville Helin for WLA DX GB-Z80 assembler.
  597. - sinamas for feedback about this document and my test ROMs.
  598.  
  599. --
  600. Shay Green <[email protected]>
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