library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity RF8x4 is
	port(s,t,d: in std_logic_vector(2 downto 0);
	lr, clk: in std_logic;
	rd: in std_logic_vector(3 downto 0);
	rs, rt: out std_logic_vector(3 downto 0));
end RF8x4;

architecture  behav of RF8x4 is
	type memory is array(0 to 7) of std_logic_vector(3 downto 0);

begin
	process is
		variable s_locn,t_locn,d_locn: natural;
		variable R: memory;
	begin
	if clk = '1' then
		 if lr = '0' then
		 	s_locn := to_integer(s);
		 	rs <= R(s_locn);
		 	t_locn := to_integer(t);
		 	rt <= R(t_locn);
		 else
		 	s_locn := to_integer(s);
		 	rs <= R(s_locn);
		 	t_locn := to_integer(t);
		 	rt <= R(t_locn);
		 	d_locn := to_integer(d);
		 	R(d_locn) := rd;
		 end if;
	end if;
	wait on clk;
	end process;


end behav;