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-- Company:
-- Engineer:
--
-- Create Date:    13:56:38 11/17/2014
-- Design Name:
-- Module Name:    alu32 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity alu32 is
    Port ( A : in  STD_LOGIC_VECTOR (31 downto 0);
           B : in  STD_LOGIC_VECTOR (31 downto 0);
              F : in  STD_LOGIC_VECTOR (2 downto 0);
           Y : out  STD_LOGIC_VECTOR (31 downto 0);
           Zero : out  STD_LOGIC);
end alu32;



architecture Behavioral of alu32 is

signal b_prime : STD_LOGIC_VECTOR (31 downto 0);
signal sum : STD_LOGIC_VECTOR (31 downto 0);
signal f_add : STD_LOGIC_VECTOR (31 downto 0);
signal slt : STD_LOGIC_VECTOR (31 downto 0);

begin
    f_add(31 downto 1) <= "0000000000000000000000000000000";
    f_add(0) <= F(2);
    sum <= std_logic_vector(signed(A) + signed(b_prime) + signed(f_add));
    slt(31 downto 1) <= "0000000000000000000000000000000";
    slt(0) <= sum(31);

    with F(2) select
        b_prime <=  NOT B when '1',
                        B when '0',
                        x"00000000" when others;

    with F(1 downto 0) select
        Y <=    A AND b_prime when "00",
                A OR b_prime when "01",
                sum when "10",
                slt when "11",
                x"00000000" when others;

    Zero <= '1' when sum = x"00000000" else '0';

end Behavioral;