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- `timescale 1ns / 1ps
- //////////////////////////////////////////////////////////////////////////////////
- // Company:
- // Engineer:
- //
- // Create Date: 11:09:07 06/26/2015
- // Design Name:
- // Module Name: p3_team8
- // Project Name:
- // Target Devices:
- // Tool versions:
- // Description:
- //
- // Dependencies:
- //
- // Revision:
- // Revision 0.01 - File Created
- // Additional Comments:
- //
- //////////////////////////////////////////////////////////////////////////////////
- module p3_team8(out,OF,op,A,B);
- input signed [15:0] A, B;
- input [3:0] op;
- output reg signed [15:0] out; //signed output
- output reg OF = 0; //overflow
- reg [31:0] register; // store results to check for overflow
- reg MSB;
- localparam MAX = 16'sb0111111111111111;
- localparam MIN = 16'sb1000000000000001;
- always @(A,B,op,MSB,register) begin
- if ( A > MAX || A < MIN || B > MAX || B < MIN ) begin
- OF = 1;
- out = 16'bX;
- end
- else
- begin
- OF = 0;
- case(op)
- 4'b0000: out = 16'bX; //do nothing
- 4'b0001: begin
- register = A+B;
- if ( A[15] == B[15]) begin
- if ( register[15] != A[15] ) begin
- OF = 1;
- out = 16'bX;
- end
- else
- out = register[15:0];
- end
- else
- out = register[15:0];
- end
- 4'b0010: {MSB,register} = A-B; //subtraction
- 4'b0011: {MSB,register} = A*4'sb0101; //multiply A by 5
- 4'b0100: {MSB,register} = A/5'sb01010; //divide A by 10
- 4'b0101: {MSB,register} = A&B; //bitwise AND
- 4'b0110: {MSB,register} = A^B; //bitwise XOR
- 4'b0111: {MSB,register} = A|B; //bitwise OR
- 4'b1000: {MSB,register} = ~A+1; //complement A
- 4'b1001: {MSB,register} = A+1; //increment
- 4'b1010: {MSB,register} = A-1; //decrement
- endcase
- end
- end
- endmodule
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