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Gil-Galad

FDS BIOS Disassembly V001

Sep 10th, 2011
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  1. ;-----------------------------------------------
  2. ; RESET - $EE24
  3. ;-----------------------------------------------
  4.  
  5. RESET: ; ADR: $EE24
  6. SEI ; Set interrupt disable.
  7. LDA #%00010000 ; 10h
  8. ; PPU setup 1.
  9. ; D0-D1: Base nametable address: $2000
  10. ; D2: VRAM increment by 1.
  11. ; D3: Sprite pattern table for 8x8 sprites: $0000
  12. ; D4: Background pattern table: $1000
  13. ; D5: Sprite size: 8x8
  14. ; D6: PPU master/slave: No effect.
  15. ; D7: NMI off at the start of vertical blanking period.
  16. STA $2000
  17. STA PPUCTRL
  18. CLD ; Clear decimal mode.
  19. LDA #%00000110 ; 06h
  20. ; PPU setup 2.
  21. ; D0: Normal color.
  22. ; D1: Show background in leftmost 8 pixels of screen.
  23. ; D2: Show sprites in leftmost 8 pixels of screen.
  24. ; D3: Background disabled.
  25. ; D4: Sprites disabled.
  26. ; D5: No red intensify.
  27. ; D6: No green intensify.
  28. ; D7: No blue intensify.
  29. STA PPUMASK
  30. STA $2001
  31.  
  32. LDX #$02
  33.  
  34. WAIT_VBL: ; ADR: $EE36
  35. ; Wait for vertical blank. At least 1 frame.
  36. LDA $2002 ; Read PPU status.
  37. BPL WAIT_VBL
  38. ; X = 02h
  39. DEX ; X = 01h
  40. ; Decrement X register.
  41. ; Burn up cycles by running the code.
  42. BNE WAIT_VBL
  43. ; X = 00h
  44. STX $4022 ; Disable timer IRQ interrupt.
  45. STX $4023 ; Disable RP2C33 I/O control. Disk functions and
  46. ; Sound disabled.
  47.  
  48. LDA #%10000011 ; 83h
  49. ; D0: Enable disk I/O
  50. ; D1: Enable sound
  51. ; D7: Unknown function
  52. ; D7 needs to be reverse engineered.
  53. STA $4023
  54.  
  55. STX PPUSCROLL_1 ; Write to shadow copy to reset scroll address latch.
  56. STX PPUSCROLL_2
  57. STX P1CTRL ; Clear player 1 controller shadow copy.
  58. STX $4016
  59. LDA #%00101110 ; 2Eh
  60. ; D0: Drive motor stopped.
  61. ; D1: No effect turning motor on.
  62. ; D2: Read disk data.
  63. ; D3: Vertical mirroring.
  64. ; D4: CRC Phase read/write data.
  65. ; D5: Unknown. Must be a 1.
  66. ; D6: Ignore data in $4024. Stream of 0's written
  67. ; to the disk.
  68. ; D7: Transfer without using IRQ.
  69. ; D5 needs reverse engineering.
  70. STA DISKCTRL
  71. STA $4025
  72.  
  73. LDA #%11111111 ; D0-D6: All bits set for data output to expansion terminal.
  74. ; D7: Battery status set for checking via $4033.
  75. STA EXT_CONNECT_O ; Shadow of $4026.
  76. STA $4026
  77.  
  78. ; X = 00h
  79. ; D7: Interrupt clear
  80. ; D6: Loop set to 0.
  81. ; D0-D3: Timer period $1AC.
  82. STX $4010
  83.  
  84. LDA #%11000000 ; C0h
  85. ; D7: Mode 1 5 step sequence
  86. ; D6: Frame interrupt cleared.
  87. STA $4017
  88.  
  89. LDA #%00001111 ; 0Fh
  90. ; D0: Square 1 channel on
  91. ; D1: Square 2 channel on
  92. ; D2: Triangle channel on
  93. ; D3: Noise channel on
  94. STA $4015
  95.  
  96. LDA #%10000000 ; 80h
  97. ; D0-D5: Volume envelope speed 0.
  98. ; D6: Volume change direction decrease.
  99. ; D7: Volume envelope mode off.
  100. STA $4080
  101.  
  102. LDA #$E8 ; Set volume and sweep envelope.
  103. STA $408A
  104.  
  105. LDX #$FF ; Set stack pointer to the top of the stack.
  106. TXS ; $01FF
  107.  
  108. LDA #$C0 ; Initialize both action on NMI and IRQ.
  109. STA ACT_NMI
  110. LDA #$80
  111. STA ACT_IRQ
  112.  
  113. LDA ACT_RESET
  114. CMP #$35 ; If 35h, disk and boot files are loaded.
  115. BNE + ; If not 35h, branch.
  116. LDA RESET_VAR
  117. CMP #$53 ; If 53h, FDS was soft reset by user.
  118. BEQ LOAD_DISK_RSET ;
  119. CMP #$AC ; If ACh, FDS was cold booted.
  120. BNE + ; If not ACh, branch.
  121. LDA #$53 ; Initialized RESET_VAR for next user reset.
  122. STA RESET_VAR
  123.  
  124. LOAD_DISK_RSET: ; ADR: $EE9B
  125. JSR RESET_PPU1
  126. CLI ; Clear interrupt disable.
  127. JMP (DISK_RESET_VECTOR) ; Go to disk reset vector.
  128.  
  129. +: ; ADR: $EEA2
  130. LDA #00 ; 00h - $00 - $F8.
  131. LDX #248 ; 248 bytes F8h
  132.  
  133. CLR_MEM_1: ; ADR: $EEA6
  134. ; Clear F8h or 248 bytes in Zero Page WRAM.
  135. ; Using a countdown decrement loop.
  136. STA $00,X
  137. DEX
  138. BNE CLR_MEM_1
  139.  
  140. ;--------------------------------------
  141. ; A = 0 X = 0
  142. STA $0301
  143. LDA #$7D
  144. STA $0300
  145. LDA #$FF
  146. STA $0302
  147.  
  148. ; Unknown initialization.
  149. ;--------------------------------------
  150.  
  151. JSR GETCTRL_STATUS
  152. LDA P1CTRL_D0_B ; Load controller 1 status bit 0.
  153. CMP #%00110000 ; 30h
  154. ; Check start and select controller buttons.
  155. ; If pressed continue on to boot test screen.
  156. BNE SKIP_BOOT_TEST ; If not 30h, skip boot test screen.
  157. LDA #$00
  158. STA ACT_RESET
  159. JMP BOOT_TEST ; Go to boot test screen.
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