port (clk_prescaler, enableConditii, rst: in std_logic;
      rez : out std_logic_vector(3 downto 0)
);

--
signal counter : std_logic_vector(3 downto 0) := (others => '0');
process (clk_prescaler, enableConditii)
begin
   if enableConditii = '1' then
		if rising_edge(clk_prescaler) then
			if rst = '1' then
				rez <= "0000";
			else
				if counter = "1001" then
					rez <= "0000";
				else counter <= counter + '1';
				end if;
			end if;
 		end if;
   end if;
end process;