fulladder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fulladder is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           cout : out  STD_LOGIC;
           s : out  STD_LOGIC);
end fulladder;

architecture Behavioral of fulladder is
-- top to bottom, left to right on slide 3 of the powerpoint.

signal SA, SB, SC : STD_LOGIC;

component andgate port (
    a: in STD_LOGIC;
    b: in STD_LOGIC;
    c: out STD_LOGIC);
end component;

component orgate port (
    a: in STD_LOGIC;
    b: in STD_LOGIC;
    c: in STD_LOGIC;
    d: out STD_LOGIC);
end component;

component xorgate port (
    a: in STD_LOGIC;
    b: in STD_LOGIC;
    c: in STD_LOGIC;
    d: out STD_LOGIC);
end component;

begin

GATEA: xorgate port map (
    a => a,
    b => b,
    c => cin,
    d => s
);

GATEB: andgate port map (
    a => a,
    b => b,
    c => SA
);

GATEC: andgate port map(
    a => a,
    b => cin,
    c => SB
);

GATED: andgate port map (
    a => b,
    b => cin,
    c => SC
);

GATEF: orgate port map (
    a => SA,
    b => SB,
    c => SC,
    d => cout
);

end Behavioral;