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-- Company:
-- Engineer:
--
-- Create Date:    10:36:57 11/22/2014
-- Design Name:
-- Module Name:    kol1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity kol1 is
    Port ( iA : in  STD_LOGIC_VECTOR (3 downto 0);
           iB : in  STD_LOGIC_VECTOR (3 downto 0);
           oRES : out  STD_LOGIC_VECTOR (7 downto 0));
end kol1;

architecture Behavioral of kol1 is
signal sMUXout3 : std_logic_vector(7 downto 0) := (others => '0');
signal sMUXout2 : std_logic_vector(7 downto 0) := (others => '0');
signal sMUXout1 : std_logic_vector(7 downto 0) := (others => '0');
signal sMUXout0 : std_logic_vector(7 downto 0) := (others => '0');

signal siA_SL3 : std_logic_vector(7 downto 0) := (others => '0');
signal siA_SL2 : std_logic_vector(7 downto 0) := (others => '0');
signal siA_SL1 : std_logic_vector(7 downto 0) := (others => '0');
signal siA_SL0 : std_logic_vector(7 downto 0) := (others => '0');

signal sSum : std_logic_vector(7 downto 0) := (others => '0');

begin
-- MUXes
sMUXout3(3 downto 0) <= iA when(iB(3) = '1')else (others => '0');
sMUXout2(3 downto 0) <= iA when(iB(2) = '1')else (others => '0');
sMUXout1(3 downto 0) <= iA when(iB(1) = '1')else (others => '0');
sMUXout0(3 downto 0) <= iA when(iB(0) = '1')else (others => '0');

-- shifters
siA_SL3 <= sMUXout3(4 downto 0) & "000"; -- x4-x3-x2-x1-x0-00-00-00
siA_SL2 <= sMUXout2(5 downto 0) & "00";  -- x5-x4-x3-x2-x1-x0-00-00
siA_SL1 <= sMUXout1(6 downto 0) & '0';   -- x6-x5-x4-x3-x2-x1-x0-00
siA_SL0 <= sMUXout0;                     -- x7-x6-x5-x4-x3-x2-x1-x0

-- adders
sSum <= siA_SL3 + (siA_SL2 + (siA_SL1 + siA_SL0));
oRES <= sSum;

end Behavioral;