Button Controller.vhd

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY Botao_FPGA IS
    PORT(
        Botao_acr : IN STD_LOGIC;
        Botao_dec : IN STD_LOGIC;
        clock     : IN STD_LOGIC;
        zCont     : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END Botao_FPGA;

ARCHITECTURE structural OF Botao_FPGA IS
    SIGNAL Contador    : STD_LOGIC_VECTOR(3 DOWNTO 0)  := "0000";
    SIGNAL Estavel_acr : STD_LOGIC := '0';
    SIGNAL Estavel_dec : STD_LOGIC := '0';

    COMPONENT cFiltro IS
        PORT(Botao   : IN STD_LOGIC;
             clock   : IN STD_LOGIC;
             Estavel : OUT STD_LOGIC);
    END COMPONENT;

    FOR ALL: cFiltro USE ENTITY work.Filtro(structural);

    SIGNAL ant_acr : STD_LOGIC := '0';
    SIGNAL ant_dec : STD_LOGIC := '0';

BEGIN

    zCont <= NOT(Contador);

    PROCESS(clock,Estavel_acr,Estavel_dec,Botao_acr,Botao_dec) IS
    BEGIN
        IF(rising_edge(clock)) THEN
            ant_acr <= Estavel_acr;
            ant_dec <= Estavel_dec;

            IF(ant_acr = '0' AND Estavel_acr = '1' AND Botao_acr = '0') THEN
                Contador <= Contador + 1;
            END IF;

            IF(ant_dec = '0' AND Estavel_dec = '1' AND Botao_dec = '0') THEN
                Contador <= Contador - 1;
            END IF;
        END IF;
    END PROCESS;

    m1: cFiltro PORT MAP(Botao_acr,clock,Estavel_acr);
    m2: cFiltro PORT MAP(Botao_dec,clock,Estavel_dec);

END structural;