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  1. ##############################################################################################################
  2. ##
  3. ##  Xilinx, Inc. 2014            www.xilinx.com  
  4. ##  Ср 2. апр 13:52:06 2014
  5. ##
  6. ##  
  7. ##############################################################################################################
  8. ##  File name :       ddr1_3.ucf
  9. ##
  10. ##  Description :     Constraints file
  11. ##                    targetted to FPGA:      xc3s500efg320
  12. ##                    Speed Grade:            -4
  13. ##                    FPGA family:            spartan3e
  14. ##                    Design Entry:           verilog
  15. ##                    Synthesis tool          ISE
  16. ##                    Time Period:            10000 ps
  17. ##                    Data width:             16
  18. ##                    Memory:                 DDR_SDRAM/Components/mt46v32m16-tg-6t-f
  19. ##                    Design:                 without Test bench
  20. ##                    DCM Used:               Enabled
  21. ##                    Data Mask:              Enabled
  22. ##
  23. ##############################################################################################################
  24.  
  25. ##############################################################################################################
  26. ## Clock constraints                                                        
  27. ##############################################################################################################
  28. NET "infrastructure_top0/sys_clk_ibuf" TNM_NET = "SYS_CLK";
  29. TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK"  10.000000  ns HIGH 50 %;
  30. ##############################################################################################################
  31.  
  32. ##############################################################################################################
  33. ## These paths are constrained to get rid of unconstrained paths.
  34. ##############################################################################################################
  35. NET "infrastructure_top0/clk_dcm0/clk" TNM_NET = "clk0";
  36. NET "top_00/data_path0/dqs_delayed_col*" TNM_NET = "dqs_clk";
  37. TIMESPEC "TS_CLK" = FROM "clk0" TO "dqs_clk"  18 ns DATAPATHONLY;
  38.  
  39. NET "infrastructure_top0/clk_dcm0/clk90" TNM_NET = "clk90";
  40. TIMESPEC "TS_CLK90" = FROM "dqs_clk" TO "clk90" 18 ns DATAPATHONLY;
  41.  
  42. NET "top_00/data_path0/data_read_controller0/gen_wr_en*fifo*_wr_en_inst/clk"
  43. TNM_NET = "fifo_we_clk";
  44. TIMESPEC "TS_WE_CLK" = FROM "dqs_clk" TO "fifo_we_clk"  5 ns DATAPATHONLY;
  45.  
  46. NET "top_00/data_path0/data_read_controller0/gen_wr_addr*fifo*_wr_addr_inst/clk" TNM_NET = "fifo_waddr_clk";
  47. TIMESPEC "TS_WADDR_CLK" = FROM "dqs_clk" TO "fifo_waddr_clk"  5 ns DATAPATHONLY;
  48.  
  49. #############################################################################################################
  50. ## Calibration Circuit Constraints
  51. #############################################################################################################
  52. ## Placement constraints for LUTS in tap delay ckt
  53. #############################################################################################################
  54. INST "infrastructure_top0/cal_top0/tap_dly0/l0" RLOC=X0Y6;
  55. INST "infrastructure_top0/cal_top0/tap_dly0/l0" U_SET = delay_calibration_chain;
  56.  
  57. INST "infrastructure_top0/cal_top0/tap_dly0/l1" RLOC=X0Y6;
  58. INST "infrastructure_top0/cal_top0/tap_dly0/l1" U_SET = delay_calibration_chain;
  59.  
  60. INST "infrastructure_top0/cal_top0/tap_dly0/l2" RLOC=X0Y7;
  61. INST "infrastructure_top0/cal_top0/tap_dly0/l2" U_SET = delay_calibration_chain;
  62.  
  63. INST "infrastructure_top0/cal_top0/tap_dly0/l3" RLOC=X0Y7;
  64. INST "infrastructure_top0/cal_top0/tap_dly0/l3" U_SET = delay_calibration_chain;
  65.  
  66. INST "infrastructure_top0/cal_top0/tap_dly0/l4" RLOC=X1Y6;
  67. INST "infrastructure_top0/cal_top0/tap_dly0/l4" U_SET = delay_calibration_chain;
  68.  
  69. INST "infrastructure_top0/cal_top0/tap_dly0/l5" RLOC=X1Y6;
  70. INST "infrastructure_top0/cal_top0/tap_dly0/l5" U_SET = delay_calibration_chain;
  71.  
  72. INST "infrastructure_top0/cal_top0/tap_dly0/l6" RLOC=X1Y7;
  73. INST "infrastructure_top0/cal_top0/tap_dly0/l6" U_SET = delay_calibration_chain;
  74.  
  75. INST "infrastructure_top0/cal_top0/tap_dly0/l7" RLOC=X1Y7;
  76. INST "infrastructure_top0/cal_top0/tap_dly0/l7" U_SET = delay_calibration_chain;
  77.  
  78. INST "infrastructure_top0/cal_top0/tap_dly0/l8" RLOC=X0Y4;
  79. INST "infrastructure_top0/cal_top0/tap_dly0/l8" U_SET = delay_calibration_chain;
  80.  
  81. INST "infrastructure_top0/cal_top0/tap_dly0/l9" RLOC=X0Y4;
  82. INST "infrastructure_top0/cal_top0/tap_dly0/l9" U_SET = delay_calibration_chain;
  83.  
  84. INST "infrastructure_top0/cal_top0/tap_dly0/l10" RLOC=X0Y5;
  85. INST "infrastructure_top0/cal_top0/tap_dly0/l10" U_SET = delay_calibration_chain;
  86.  
  87. INST "infrastructure_top0/cal_top0/tap_dly0/l11" RLOC=X0Y5;
  88. INST "infrastructure_top0/cal_top0/tap_dly0/l11" U_SET = delay_calibration_chain;
  89.  
  90. INST "infrastructure_top0/cal_top0/tap_dly0/l12" RLOC=X1Y4;
  91. INST "infrastructure_top0/cal_top0/tap_dly0/l12" U_SET = delay_calibration_chain;
  92.  
  93. INST "infrastructure_top0/cal_top0/tap_dly0/l13" RLOC=X1Y4;
  94. INST "infrastructure_top0/cal_top0/tap_dly0/l13" U_SET = delay_calibration_chain;
  95.  
  96. INST "infrastructure_top0/cal_top0/tap_dly0/l14" RLOC=X1Y5;
  97. INST "infrastructure_top0/cal_top0/tap_dly0/l14" U_SET = delay_calibration_chain;
  98.  
  99. INST "infrastructure_top0/cal_top0/tap_dly0/l15" RLOC=X1Y5;
  100. INST "infrastructure_top0/cal_top0/tap_dly0/l15" U_SET = delay_calibration_chain;
  101.  
  102. INST "infrastructure_top0/cal_top0/tap_dly0/l16" RLOC=X0Y2;
  103. INST "infrastructure_top0/cal_top0/tap_dly0/l16" U_SET = delay_calibration_chain;
  104.  
  105. INST "infrastructure_top0/cal_top0/tap_dly0/l17" RLOC=X0Y2;
  106. INST "infrastructure_top0/cal_top0/tap_dly0/l17" U_SET = delay_calibration_chain;
  107.  
  108. INST "infrastructure_top0/cal_top0/tap_dly0/l18" RLOC=X0Y3;
  109. INST "infrastructure_top0/cal_top0/tap_dly0/l18" U_SET = delay_calibration_chain;
  110.  
  111. INST "infrastructure_top0/cal_top0/tap_dly0/l19" RLOC=X0Y3;
  112. INST "infrastructure_top0/cal_top0/tap_dly0/l19" U_SET = delay_calibration_chain;
  113.  
  114. INST "infrastructure_top0/cal_top0/tap_dly0/l20" RLOC=X1Y2;
  115. INST "infrastructure_top0/cal_top0/tap_dly0/l20" U_SET = delay_calibration_chain;
  116.  
  117. INST "infrastructure_top0/cal_top0/tap_dly0/l21" RLOC=X1Y2;
  118. INST "infrastructure_top0/cal_top0/tap_dly0/l21" U_SET = delay_calibration_chain;
  119.  
  120. INST "infrastructure_top0/cal_top0/tap_dly0/l22" RLOC=X1Y3;
  121. INST "infrastructure_top0/cal_top0/tap_dly0/l22" U_SET = delay_calibration_chain;
  122.  
  123. INST "infrastructure_top0/cal_top0/tap_dly0/l23" RLOC=X1Y3;
  124. INST "infrastructure_top0/cal_top0/tap_dly0/l23" U_SET = delay_calibration_chain;
  125.  
  126. INST "infrastructure_top0/cal_top0/tap_dly0/l24" RLOC=X0Y0;
  127. INST "infrastructure_top0/cal_top0/tap_dly0/l24" U_SET = delay_calibration_chain;
  128.  
  129. INST "infrastructure_top0/cal_top0/tap_dly0/l25" RLOC=X0Y0;
  130. INST "infrastructure_top0/cal_top0/tap_dly0/l25" U_SET = delay_calibration_chain;
  131.  
  132. INST "infrastructure_top0/cal_top0/tap_dly0/l26" RLOC=X0Y1;
  133. INST "infrastructure_top0/cal_top0/tap_dly0/l26" U_SET = delay_calibration_chain;
  134.  
  135. INST "infrastructure_top0/cal_top0/tap_dly0/l27" RLOC=X0Y1;
  136. INST "infrastructure_top0/cal_top0/tap_dly0/l27" U_SET = delay_calibration_chain;
  137.  
  138. INST "infrastructure_top0/cal_top0/tap_dly0/l28" RLOC=X1Y0;
  139. INST "infrastructure_top0/cal_top0/tap_dly0/l28" U_SET = delay_calibration_chain;
  140.  
  141. INST "infrastructure_top0/cal_top0/tap_dly0/l29" RLOC=X1Y0;
  142. INST "infrastructure_top0/cal_top0/tap_dly0/l29" U_SET = delay_calibration_chain;
  143.  
  144. INST "infrastructure_top0/cal_top0/tap_dly0/l30" RLOC=X1Y1;
  145. INST "infrastructure_top0/cal_top0/tap_dly0/l30" U_SET = delay_calibration_chain;
  146.  
  147. INST "infrastructure_top0/cal_top0/tap_dly0/l31" RLOC=X1Y1;
  148. INST "infrastructure_top0/cal_top0/tap_dly0/l31" U_SET = delay_calibration_chain;
  149.  
  150. #################################################################################################################
  151. # Placement constraints for first stage flops in tap delay ckt
  152. #################################################################################################################
  153. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[0].r" RLOC=X0Y6;
  154. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[0].r" U_SET = delay_calibration_chain;
  155.  
  156. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[1].r" RLOC=X0Y6;
  157. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[1].r" U_SET = delay_calibration_chain;
  158.  
  159. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[2].r" RLOC=X0Y7;
  160. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[2].r" U_SET = delay_calibration_chain;
  161.  
  162. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[3].r" RLOC=X0Y7;
  163. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[3].r" U_SET = delay_calibration_chain;
  164.  
  165. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[4].r" RLOC=X1Y6;
  166. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[4].r" U_SET = delay_calibration_chain;
  167.  
  168. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[5].r" RLOC=X1Y6;
  169. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[5].r" U_SET = delay_calibration_chain;
  170.  
  171. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[6].r" RLOC=X1Y7;
  172. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[6].r" U_SET = delay_calibration_chain;
  173.  
  174. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[7].r" RLOC=X1Y7;
  175. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[7].r" U_SET = delay_calibration_chain;
  176.  
  177. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[8].r" RLOC=X0Y4;
  178. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[8].r" U_SET = delay_calibration_chain;
  179.  
  180. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[9].r" RLOC=X0Y4;
  181. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[9].r" U_SET = delay_calibration_chain;
  182.  
  183. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[10].r" RLOC=X0Y5;
  184. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[10].r" U_SET = delay_calibration_chain;
  185.  
  186. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[11].r" RLOC=X0Y5;
  187. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[11].r" U_SET = delay_calibration_chain;
  188.  
  189. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[12].r" RLOC=X1Y4;
  190. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[12].r" U_SET = delay_calibration_chain;
  191.  
  192. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[13].r" RLOC=X1Y4;
  193. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[13].r" U_SET = delay_calibration_chain;
  194.  
  195. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[14].r" RLOC=X1Y5;
  196. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[14].r" U_SET = delay_calibration_chain;
  197.  
  198. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[15].r" RLOC=X1Y5;
  199. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[15].r" U_SET = delay_calibration_chain;
  200.  
  201. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[16].r" RLOC=X0Y2;
  202. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[16].r" U_SET = delay_calibration_chain;
  203.  
  204. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[17].r" RLOC=X0Y2;
  205. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[17].r" U_SET = delay_calibration_chain;
  206.  
  207. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[18].r" RLOC=X0Y3;
  208. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[18].r" U_SET = delay_calibration_chain;
  209.  
  210. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[19].r" RLOC=X0Y3;
  211. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[19].r" U_SET = delay_calibration_chain;
  212.  
  213. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[20].r" RLOC=X1Y2;
  214. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[20].r" U_SET = delay_calibration_chain;
  215.  
  216. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[21].r" RLOC=X1Y2;
  217. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[21].r" U_SET = delay_calibration_chain;
  218.  
  219. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[22].r" RLOC=X1Y3;
  220. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[22].r" U_SET = delay_calibration_chain;
  221.  
  222. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[23].r" RLOC=X1Y3;
  223. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[23].r" U_SET = delay_calibration_chain;
  224.  
  225. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[24].r" RLOC=X0Y0;
  226. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[24].r" U_SET = delay_calibration_chain;
  227.  
  228. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[25].r" RLOC=X0Y0;
  229. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[25].r" U_SET = delay_calibration_chain;
  230.  
  231. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[26].r" RLOC=X0Y1;
  232. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[26].r" U_SET = delay_calibration_chain;
  233.  
  234. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[27].r" RLOC=X0Y1;
  235. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[27].r" U_SET = delay_calibration_chain;
  236.  
  237. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[28].r" RLOC=X1Y0;
  238. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[28].r" U_SET = delay_calibration_chain;
  239.  
  240. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[29].r" RLOC=X1Y0;
  241. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[29].r" U_SET = delay_calibration_chain;
  242.  
  243. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[30].r" RLOC=X1Y1;
  244. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[30].r" U_SET = delay_calibration_chain;
  245.  
  246. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[31].r" RLOC=X1Y1;
  247. INST "infrastructure_top0/cal_top0/tap_dly0/gen_tap1[31].r" U_SET = delay_calibration_chain;
  248.  
  249. #####################################################################################################################
  250. ## BEL constraints for LUTS in tap delay ckt
  251. #####################################################################################################################
  252. INST "infrastructure_top0/cal_top0/tap_dly0/l0"  BEL= G;
  253. INST "infrastructure_top0/cal_top0/tap_dly0/l1"  BEL= F;
  254. INST "infrastructure_top0/cal_top0/tap_dly0/l2"  BEL= G;
  255. INST "infrastructure_top0/cal_top0/tap_dly0/l3"  BEL= F;
  256. INST "infrastructure_top0/cal_top0/tap_dly0/l4"  BEL= G;
  257. INST "infrastructure_top0/cal_top0/tap_dly0/l5"  BEL= F;
  258. INST "infrastructure_top0/cal_top0/tap_dly0/l6"  BEL= G;
  259. INST "infrastructure_top0/cal_top0/tap_dly0/l7"  BEL= F;
  260. INST "infrastructure_top0/cal_top0/tap_dly0/l8"  BEL= G;
  261. INST "infrastructure_top0/cal_top0/tap_dly0/l9"  BEL= F;
  262. INST "infrastructure_top0/cal_top0/tap_dly0/l10" BEL= G;
  263. INST "infrastructure_top0/cal_top0/tap_dly0/l11" BEL= F;
  264. INST "infrastructure_top0/cal_top0/tap_dly0/l12" BEL= G;
  265. INST "infrastructure_top0/cal_top0/tap_dly0/l13" BEL= F;
  266. INST "infrastructure_top0/cal_top0/tap_dly0/l14" BEL= G;
  267. INST "infrastructure_top0/cal_top0/tap_dly0/l15" BEL= F;
  268. INST "infrastructure_top0/cal_top0/tap_dly0/l16" BEL= G;
  269. INST "infrastructure_top0/cal_top0/tap_dly0/l17" BEL= F;
  270. INST "infrastructure_top0/cal_top0/tap_dly0/l18" BEL= G;
  271. INST "infrastructure_top0/cal_top0/tap_dly0/l19" BEL= F;
  272. INST "infrastructure_top0/cal_top0/tap_dly0/l20" BEL= G;
  273. INST "infrastructure_top0/cal_top0/tap_dly0/l21" BEL= F;
  274. INST "infrastructure_top0/cal_top0/tap_dly0/l22" BEL= G;
  275. INST "infrastructure_top0/cal_top0/tap_dly0/l23" BEL= F;
  276. INST "infrastructure_top0/cal_top0/tap_dly0/l24" BEL= G;
  277. INST "infrastructure_top0/cal_top0/tap_dly0/l25" BEL= F;  
  278. INST "infrastructure_top0/cal_top0/tap_dly0/l26" BEL= G;
  279. INST "infrastructure_top0/cal_top0/tap_dly0/l27" BEL= F;
  280. INST "infrastructure_top0/cal_top0/tap_dly0/l28" BEL= G;
  281. INST "infrastructure_top0/cal_top0/tap_dly0/l29" BEL= F;
  282. INST "infrastructure_top0/cal_top0/tap_dly0/l30" BEL= G;
  283. INST "infrastructure_top0/cal_top0/tap_dly0/l31" BEL= F;
  284.  
  285.  
  286.  
  287. ##############################################################################################################
  288. ## RLOC Origin constraint for LUT delay calibration chain.
  289. ##############################################################################################################
  290. INST "infrastructure_top0/cal_top0/tap_dly0/l0" RLOC_ORIGIN = X28Y70;
  291.  
  292. ##############################################################################################################
  293. ## Area Group Constraint For tap_dly and cal_ctl module.
  294. ##############################################################################################################
  295. INST "infrastructure_top0/cal_top0/cal_ctl0" AREA_GROUP = cal_ctl;
  296. INST "infrastructure_top0/cal_top0/tap_dly0" AREA_GROUP = cal_ctl;
  297. AREA_GROUP "cal_ctl" RANGE = SLICE_X28Y70:SLICE_X39Y83;
  298. AREA_GROUP "cal_ctl" GROUP = CLOSED;
  299.  
  300. ##############################################################################################################
  301.  
  302. #***********************************************************************************************************#
  303. #                        CONTROLLER 0                                                                  
  304. #***********************************************************************************************************#
  305.  
  306. ##############################################################################################################
  307. # I/O STANDARDS                                                        
  308. ##############################################################################################################
  309. NET  "cntrl0_ddr_dq[*]"                         IOSTANDARD = SSTL2_I;
  310. NET  "cntrl0_ddr_a[*]"                          IOSTANDARD = SSTL2_I;
  311. NET  "cntrl0_ddr_ba[*]"                         IOSTANDARD = SSTL2_I;
  312. NET  "cntrl0_ddr_cke"                           IOSTANDARD = SSTL2_I;
  313. NET  "cntrl0_ddr_cs_n"                          IOSTANDARD = SSTL2_I;
  314. NET  "cntrl0_ddr_ras_n"                         IOSTANDARD = SSTL2_I;
  315. NET  "cntrl0_ddr_cas_n"                         IOSTANDARD = SSTL2_I;
  316. NET  "cntrl0_ddr_we_n"                          IOSTANDARD = SSTL2_I;
  317. NET  "cntrl0_ddr_dm[*]"                         IOSTANDARD = SSTL2_I;
  318. NET  "cntrl0_rst_dqs_div_in"                    IOSTANDARD = SSTL2_I;
  319. NET  "cntrl0_rst_dqs_div_out"                   IOSTANDARD = SSTL2_I;
  320. NET  "sys_clkb"                                 IOSTANDARD = LVDS_25;
  321. NET  "sys_clk"                                  IOSTANDARD = LVDS_25;
  322. NET  "reset_in_n"                               IOSTANDARD = LVCMOS25;
  323. NET  "cntrl0_ddr_dqs[*]"                        IOSTANDARD = SSTL2_I;
  324. NET  "cntrl0_ddr_ck[*]"                         IOSTANDARD = DIFF_SSTL2_I;
  325. NET  "cntrl0_ddr_ck_n[*]"                       IOSTANDARD = DIFF_SSTL2_I;
  326.  
  327.  
  328. ##############################################################################################################
  329. # Pin Location Constraints for System clock signals
  330. ##############################################################################################################
  331. NET  "sys_clkb"                                   LOC = "D9" ;     #bank 0
  332. NET  "sys_clk"                                    LOC = "C9" ;     #bank 0
  333.  
  334. ##############################################################################################################
  335. # Pin Location Constraints for Clock,Masks, Address, and Controls
  336. ##############################################################################################################
  337. NET  "cntrl0_ddr_ck[0]"                          LOC = "J5" ;     #bank 3
  338. NET  "cntrl0_ddr_ck_n[0]"                          LOC = "J4" ;     #bank 3
  339. NET  "cntrl0_ddr_dm[0]"                          LOC = "L1" ;     #bank 3
  340. NET  "cntrl0_ddr_dm[1]"                          LOC = "H2" ;     #bank 3
  341. NET  "cntrl0_ddr_a[12]"                           LOC = "H4" ;     #bank 3
  342. NET  "cntrl0_ddr_a[11]"                           LOC = "H3" ;     #bank 3
  343. NET  "cntrl0_ddr_a[10]"                           LOC = "H6" ;     #bank 3
  344. NET  "cntrl0_ddr_a[9]"                            LOC = "H5" ;     #bank 3
  345. NET  "cntrl0_ddr_a[8]"                            LOC = "G6" ;     #bank 3
  346. NET  "cntrl0_ddr_a[7]"                            LOC = "G5" ;     #bank 3
  347. NET  "cntrl0_ddr_a[6]"                            LOC = "F1" ;     #bank 3
  348. NET  "cntrl0_ddr_a[5]"                            LOC = "F2" ;     #bank 3
  349. NET  "cntrl0_ddr_a[4]"                            LOC = "E2" ;     #bank 3
  350. NET  "cntrl0_ddr_a[3]"                            LOC = "E1" ;     #bank 3
  351. NET  "cntrl0_ddr_a[2]"                            LOC = "C1" ;     #bank 3
  352. NET  "cntrl0_ddr_a[1]"                            LOC = "C2" ;     #bank 3
  353. NET  "cntrl0_ddr_a[0]"                            LOC = "G3" ;     #bank 3
  354. NET  "cntrl0_ddr_ba[1]"                           LOC = "F4" ;     #bank 3
  355. NET  "cntrl0_ddr_ba[0]"                           LOC = "D1" ;     #bank 3
  356. NET  "cntrl0_ddr_cke"                             LOC = "B3" ;     #bank 0
  357. NET  "cntrl0_ddr_cs_n"                            LOC = "C3" ;     #bank 0
  358. NET  "cntrl0_ddr_ras_n"                           LOC = "B4" ;     #bank 0
  359. NET  "cntrl0_ddr_cas_n"                           LOC = "A4" ;     #bank 0
  360. NET  "cntrl0_ddr_we_n"                            LOC = "C4" ;     #bank 0
  361. NET  "reset_in_n"                                 LOC = "C5" ;     #bank 0
  362.  
  363. ##############################################################################################################
  364. ## MAXDELAY constraints
  365. ##############################################################################################################
  366.  
  367. ##############################################################################################################
  368. ## Constraint to have the tap delay inverter connection wire length to be the same and minimum to get
  369. ## accurate calibration of tap delays. The following constraints are independent of frequency.
  370. ##############################################################################################################
  371. NET "infrastructure_top0/cal_top0/tap_dly0/tap[7]"  MAXDELAY = 400 ps;
  372. NET "infrastructure_top0/cal_top0/tap_dly0/tap[15]"  MAXDELAY = 400 ps;
  373. NET "infrastructure_top0/cal_top0/tap_dly0/tap[23]"  MAXDELAY = 400 ps;
  374.  
  375. ##############################################################################################################
  376. ## MAXDELAY constraint on inter LUT delay elements. This constraint is required to minimize the
  377. ## wire delays between the LUTs.
  378. ##############################################################################################################
  379. NET "top_00/data_path0/data_read_controller0/gen_delay*dqs_delay_col*/delay*"  MAXDELAY = 200 ps;
  380. NET "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/delay*"  MAXDELAY = 200 ps;
  381.  
  382. ##############################################################################################################
  383. ## Constraint from the dqs PAD to input of LUT delay element.
  384. ##############################################################################################################
  385. NET "top_00/dqs_int_delay_in*" MAXDELAY = 494 ps;
  386.  
  387. ##############################################################################################################
  388. ## Constraint from rst_dqs_div_in PAD to input of LUT delay element.
  389. ##############################################################################################################
  390. NET "top_00/dqs_div_rst" MAXDELAY = 460 ps;
  391.  
  392. ##############################################################################################################
  393. ## Following are the MAXDELAY constraints on delayed rst_dqs_div net and fifo write enable signals.
  394. ## These constraints are required since these paths are not covered by timing analysis. The requirement is total
  395. ## delay on delayed rst_dqs_div and fifo_wr_en nets should not exceed the clock period.
  396. ##############################################################################################################
  397. NET "top_00/data_path0/data_read_controller0/rst_dqs_div"  MAXDELAY = 4000 ps;
  398. NET "top_00/data_path0/data_read0/fifo*_wr_en*"                    MAXDELAY = 4000 ps;
  399.  
  400. ##############################################################################################################
  401. ## The MAXDELAY value on fifo write address should be less than clock period. This constraint is
  402. ## required since this path is not covered by timing analysis.
  403. ##############################################################################################################
  404. NET "top_00/data_path0/data_read0/fifo*_wr_addr[*]"           MAXDELAY = 8500 ps;
  405.  
  406. ##############################################################################################################
  407.  
  408. ##############################################################################################################
  409. ##  constraints for bit cntrl0_ddr_dq, 1, location in tile: 0
  410. ##############################################################################################################
  411. NET "cntrl0_ddr_dq[1]" LOC = "T1";     #bank 3
  412. INST "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit1"   LOC = SLICE_X0Y2;
  413. INST "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit1" LOC = SLICE_X0Y3;
  414.  
  415. ##############################################################################################################
  416. ##  constraints for bit cntrl0_ddr_dq, 0, location in tile: 0
  417. ##############################################################################################################
  418. NET "cntrl0_ddr_dq[0]" LOC = "T2";     #bank 3
  419. INST "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit0"   LOC = SLICE_X2Y2;
  420. INST "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit0" LOC = SLICE_X2Y3;
  421.  
  422. ##############################################################################################################
  423. ##  constraints for bit cntrl0_ddr_dq, 3, location in tile: 0
  424. ##############################################################################################################
  425. NET "cntrl0_ddr_dq[3]" LOC = "R2";     #bank 3
  426. INST "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit3"   LOC = SLICE_X0Y6;
  427. INST "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit3" LOC = SLICE_X0Y7;
  428.  
  429. ##############################################################################################################
  430. ##  constraints for bit cntrl0_ddr_dq, 2, location in tile: 0
  431. ##############################################################################################################
  432. NET "cntrl0_ddr_dq[2]" LOC = "R3";     #bank 3
  433. INST "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit2"   LOC = SLICE_X2Y6;
  434. INST "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit2" LOC = SLICE_X2Y7;
  435.  
  436. ##############################################################################################################
  437. ##  constraints for bit cntrl0_ddr_dqs, 0, location in tile: 0
  438. ##############################################################################################################
  439. NET "cntrl0_ddr_dqs[0]" LOC = "P2";     #bank 3
  440.  
  441. ##############################################################################################################
  442. ## LUT location constraints for dqs_delayed_col0
  443. ##############################################################################################################
  444. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one" LOC = SLICE_X0Y13;
  445. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one" BEL = F;
  446. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two" LOC = SLICE_X0Y13;
  447. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two" BEL = G;
  448. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three" LOC = SLICE_X0Y12;
  449. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three" BEL = G;
  450. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four" LOC = SLICE_X0Y12;
  451. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four" BEL = F;
  452. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five" LOC = SLICE_X1Y13;
  453. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five" BEL = G;
  454. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six" LOC = SLICE_X1Y12;
  455. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six" BEL = G;
  456.  
  457. ##############################################################################################################
  458. ## LUT location constraints for dqs_delayed_col1
  459. ##############################################################################################################
  460. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one" LOC = SLICE_X2Y13;
  461. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one" BEL = F;
  462. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two" LOC = SLICE_X2Y13;
  463. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two" BEL = G;
  464. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three" LOC = SLICE_X2Y12;
  465. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three" BEL = G;
  466. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four" LOC = SLICE_X2Y12;
  467. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four" BEL = F;
  468. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five" LOC = SLICE_X3Y13;
  469. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five" BEL = G;
  470. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six" LOC = SLICE_X3Y12;
  471. INST "top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six" BEL = G;
  472.  
  473. ##############################################################################################################
  474. ## Slice location constraints for Fifo write address and write enable
  475. ##############################################################################################################
  476. INST "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit0" LOC = SLICE_X3Y8;
  477. INST "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit1" LOC = SLICE_X3Y8;
  478. INST "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit2" LOC = SLICE_X3Y9;
  479. INST "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit3" LOC = SLICE_X3Y9;
  480. INST "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit0" LOC = SLICE_X1Y8;
  481. INST "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit1" LOC = SLICE_X1Y8;
  482. INST "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit2" LOC = SLICE_X1Y9;
  483. INST "top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit3" LOC = SLICE_X1Y9;
  484. INST "top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_0_wr_en_inst" LOC = SLICE_X3Y11;
  485. INST "top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_1_wr_en_inst" LOC = SLICE_X1Y11;
  486.  
  487. ##############################################################################################################
  488. ##  constraints for bit cntrl0_ddr_dq, 5, location in tile: 0
  489. ##############################################################################################################
  490. NET "cntrl0_ddr_dq[5]" LOC = "N5";     #bank 3
  491. INST "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit5"   LOC = SLICE_X0Y16;
  492. INST "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit5" LOC = SLICE_X0Y17;
  493.  
  494. ##############################################################################################################
  495. ##  constraints for bit cntrl0_ddr_dq, 4, location in tile: 0
  496. ##############################################################################################################
  497. NET "cntrl0_ddr_dq[4]" LOC = "N4";     #bank 3
  498. INST "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit4"   LOC = SLICE_X2Y16;
  499. INST "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit4" LOC = SLICE_X2Y17;
  500.  
  501. ##############################################################################################################
  502. ##  constraints for bit cntrl0_ddr_dq, 7, location in tile: 0
  503. ##############################################################################################################
  504. NET "cntrl0_ddr_dq[7]" LOC = "M6";     #bank 3
  505. INST "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit7"   LOC = SLICE_X0Y20;
  506. INST "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit7" LOC = SLICE_X0Y21;
  507.  
  508. ##############################################################################################################
  509. ##  constraints for bit cntrl0_ddr_dq, 6, location in tile: 0
  510. ##############################################################################################################
  511. NET "cntrl0_ddr_dq[6]" LOC = "M5";     #bank 3
  512. INST "top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit6"   LOC = SLICE_X2Y20;
  513. INST "top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit6" LOC = SLICE_X2Y21;
  514.  
  515. ##############################################################################################################
  516. ##  constraints for bit cntrl0_ddr_dq, 8, location in tile: 0
  517. ##############################################################################################################
  518. NET "cntrl0_ddr_dq[8]" LOC = "L6";     #bank 3
  519. INST "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit0"   LOC = SLICE_X2Y28;
  520. INST "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit0" LOC = SLICE_X2Y29;
  521.  
  522. ##############################################################################################################
  523. ##  constraints for bit cntrl0_ddr_dq, 9, location in tile: 0
  524. ##############################################################################################################
  525. NET "cntrl0_ddr_dq[9]" LOC = "L4";     #bank 3
  526. INST "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit1"   LOC = SLICE_X0Y32;
  527. INST "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit1" LOC = SLICE_X0Y33;
  528.  
  529. ##############################################################################################################
  530. ##  constraints for bit cntrl0_ddr_dq, 10, location in tile: 0
  531. ##############################################################################################################
  532. NET "cntrl0_ddr_dq[10]" LOC = "L3";     #bank 3
  533. INST "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit2"   LOC = SLICE_X2Y32;
  534. INST "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit2" LOC = SLICE_X2Y33;
  535.  
  536. ##############################################################################################################
  537. ##  constraints for bit cntrl0_ddr_dq, 11, location in tile: 0
  538. ##############################################################################################################
  539. NET "cntrl0_ddr_dq[11]" LOC = "L2";     #bank 3
  540. INST "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit3"   LOC = SLICE_X0Y36;
  541. INST "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit3" LOC = SLICE_X0Y37;
  542.  
  543. ##############################################################################################################
  544. ##  constraints for bit cntrl0_ddr_dqs, 1, location in tile: 0
  545. ##############################################################################################################
  546. NET "cntrl0_ddr_dqs[1]" LOC = "K6";     #bank 3
  547.  
  548. ##############################################################################################################
  549. ## LUT location constraints for dqs_delayed_col0
  550. ##############################################################################################################
  551. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one" LOC = SLICE_X0Y41;
  552. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one" BEL = F;
  553. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two" LOC = SLICE_X0Y41;
  554. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two" BEL = G;
  555. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three" LOC = SLICE_X0Y40;
  556. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three" BEL = G;
  557. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four" LOC = SLICE_X0Y40;
  558. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four" BEL = F;
  559. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five" LOC = SLICE_X1Y41;
  560. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five" BEL = G;
  561. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six" LOC = SLICE_X1Y40;
  562. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six" BEL = G;
  563.  
  564. ##############################################################################################################
  565. ## LUT location constraints for dqs_delayed_col1
  566. ##############################################################################################################
  567. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one" LOC = SLICE_X2Y41;
  568. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one" BEL = F;
  569. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two" LOC = SLICE_X2Y41;
  570. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two" BEL = G;
  571. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three" LOC = SLICE_X2Y40;
  572. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three" BEL = G;
  573. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four" LOC = SLICE_X2Y40;
  574. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four" BEL = F;
  575. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five" LOC = SLICE_X3Y41;
  576. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five" BEL = G;
  577. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six" LOC = SLICE_X3Y40;
  578. INST "top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six" BEL = G;
  579.  
  580. ##############################################################################################################
  581. ## Slice location constraints for Fifo write address and write enable
  582. ##############################################################################################################
  583. INST "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit0" LOC = SLICE_X3Y36;
  584. INST "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit1" LOC = SLICE_X3Y36;
  585. INST "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit2" LOC = SLICE_X3Y37;
  586. INST "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit3" LOC = SLICE_X3Y37;
  587. INST "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit0" LOC = SLICE_X1Y36;
  588. INST "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit1" LOC = SLICE_X1Y36;
  589. INST "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit2" LOC = SLICE_X1Y37;
  590. INST "top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit3" LOC = SLICE_X1Y37;
  591. INST "top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_0_wr_en_inst" LOC = SLICE_X3Y39;
  592. INST "top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_1_wr_en_inst" LOC = SLICE_X1Y39;
  593.  
  594. ##############################################################################################################
  595. ##  constraints for bit cntrl0_ddr_dq, 13, location in tile: 0
  596. ##############################################################################################################
  597. NET "cntrl0_ddr_dq[13]" LOC = "K4";     #bank 3
  598. INST "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit5"   LOC = SLICE_X0Y44;
  599. INST "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit5" LOC = SLICE_X0Y45;
  600.  
  601. ##############################################################################################################
  602. ##  constraints for bit cntrl0_ddr_dq, 12, location in tile: 0
  603. ##############################################################################################################
  604. NET "cntrl0_ddr_dq[12]" LOC = "K3";     #bank 3
  605. INST "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit4"   LOC = SLICE_X2Y44;
  606. INST "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit4" LOC = SLICE_X2Y45;
  607.  
  608. ##############################################################################################################
  609. ##  constraints for bit cntrl0_ddr_dq, 15, location in tile: 0
  610. ##############################################################################################################
  611. NET "cntrl0_ddr_dq[15]" LOC = "J2";     #bank 3
  612. INST "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit7"   LOC = SLICE_X0Y48;
  613. INST "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit7" LOC = SLICE_X0Y49;
  614.  
  615. ##############################################################################################################
  616. ##  constraints for bit cntrl0_ddr_dq, 14, location in tile: 0
  617. ##############################################################################################################
  618. NET "cntrl0_ddr_dq[14]" LOC = "J1";     #bank 3
  619. INST "top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit6"   LOC = SLICE_X2Y48;
  620. INST "top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit6" LOC = SLICE_X2Y49;
  621.  
  622. ##############################################################################################################
  623. ##  constraints for bit cntrl0_rst_dqs_div_in, 1, location in tile: 1
  624. ##############################################################################################################
  625. NET "cntrl0_rst_dqs_div_in" LOC = "M4";     #bank 3
  626.  
  627. ##############################################################################################################
  628. ## Slice location constraints for delayed rst_dqs_div signal
  629. ##############################################################################################################
  630. INST "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/one" LOC = SLICE_X0Y25;
  631. INST "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/one" BEL = F;
  632. INST "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/two" LOC = SLICE_X0Y24;
  633. INST "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/two" BEL = G;
  634. INST "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/three" LOC = SLICE_X0Y25;
  635. INST "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/three" BEL = G;
  636. INST "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/four" LOC = SLICE_X1Y24;
  637. INST "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/four" BEL = F;
  638. INST "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/five" LOC = SLICE_X1Y24;
  639. INST "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/five" BEL = G;
  640. INST "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/six" LOC = SLICE_X1Y25;
  641. INST "top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/six" BEL = G;
  642.  
  643. ##############################################################################################################
  644. ##  constraints for bit cntrl0_rst_dqs_div_out, 1, location in tile: 0
  645. ##############################################################################################################
  646. NET "cntrl0_rst_dqs_div_out" LOC = "M3";     #bank 3
  647.  
  648. ##############################################################################################################
  649. ## Location constraint for rst_dqs_div_r flop in the controller. This is to be placed close the PAD
  650. ## that drives the rst_dqs_div _out signal to meet the timing.
  651. ##############################################################################################################
  652. INST "top_00/controller0/rst_dqs_div_r" LOC = SLICE_X12Y25;
  653. ##############################################################################################################
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