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  1. /dts-v1/;
  2.  
  3. #include "am33xx.dtsi"
  4. #include <dt-bindings/pwm/pwm.h>
  5.  
  6. / {
  7. model = "Just model";
  8. compatible = "company,family", "ti,am33xx";
  9.  
  10. cpus {
  11. cpu@0 {
  12. cpu0-supply = <&vdd1_reg>;
  13. };
  14. };
  15.  
  16. memory {
  17. device_type = "memory";
  18. reg = <0x80000000 0x10000000>; /* 256 MB */
  19. };
  20.  
  21. vbat: fixedregulator@0 {
  22. compatible = "regulator-fixed";
  23. regulator-name = "vbat";
  24. regulator-min-microvolt = <5000000>;
  25. regulator-max-microvolt = <5000000>;
  26. regulator-boot-on;
  27. };
  28.  
  29. lis3_reg: fixedregulator@1 {
  30. compatible = "regulator-fixed";
  31. regulator-name = "lis3_reg";
  32. regulator-boot-on;
  33. };
  34.  
  35. wl12xx_vmmc: fixedregulator@2 {
  36. pinctrl-names = "default";
  37. pinctrl-0 = <&wl12xx_gpio>;
  38. compatible = "regulator-fixed";
  39. regulator-name = "vwl1271";
  40. regulator-min-microvolt = <3300000>;
  41. regulator-max-microvolt = <3300000>;
  42. gpio = <&gpio3 8 0>;
  43. startup-delay-us = <70000>;
  44. enable-active-high;
  45. };
  46. };
  47.  
  48. &am33xx_pinmux {
  49. mmc2_pins: pinmux_mmc2_pins {
  50. pinctrl-single,pins = <
  51. 0x020 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */
  52. 0x024 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */
  53. 0x028 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */
  54. 0x02c (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */
  55. 0x080 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */
  56. 0x084 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */
  57. 0x1e4 (PIN_INPUT_PULLUP | MUX_MODE7) /* emu0.gpio3[7] */
  58. >;
  59. };
  60.  
  61. wl12xx_gpio: pinmux_wl12xx_gpio {
  62. pinctrl-single,pins = <
  63. 0x1e8 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */
  64. >;
  65. };
  66.  
  67. tps65910_pins: pinmux_tps65910_pins {
  68. pinctrl-single,pins = <
  69. 0x078 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */
  70. >;
  71. };
  72.  
  73. tca6416_pins: pinmux_tca6416_pins {
  74. pinctrl-single,pins = <
  75. 0x1b4 (PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */
  76. >;
  77. };
  78.  
  79. i2c1_pins: pinmux_i2c1_pins {
  80. pinctrl-single,pins = <
  81. 0x158 0x2a /* spi0_d1.i2c1_sda_mux3, INPUT | MODE2 */
  82. 0x15c 0x2a /* spi0_cs0.i2c1_scl_mux3, INPUT | MODE2 */
  83. >;
  84. };
  85.  
  86. dcan1_pins: pinmux_dcan1_pins {
  87. pinctrl-single,pins = <
  88. 0x168 0x0a /* uart0_ctsn.dcan1_tx_mux0, OUTPUT | MODE2 */
  89. 0x16c 0x2a /* uart0_rtsn.dcan1_rx_mux0, INPUT | MODE2 */
  90. >;
  91. };
  92.  
  93. uart0_pins: pinmux_uart0_pins {
  94. pinctrl-single,pins = <
  95. 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
  96. 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
  97. >;
  98. };
  99.  
  100. uart1_pins: pinmux_uart1_pins {
  101. pinctrl-single,pins = <
  102. /*0x178 0x28*/ /* uart1_ctsn, INPUT | MODE0 */
  103. /*0x17c 0x08*/ /* uart1_rtsn, OUTPUT | MODE0 */
  104. 0x180 0x28 /* uart1_rxd, INPUT | MODE0 */
  105. 0x184 0x28 /* uart1_txd, INPUT | MODE0 */
  106. 0x178 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn, INPUT | MODE0 */
  107. 0x17c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn, OUTPUT | MODE0 */
  108. 0x0e0 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */
  109. 0x0e4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */
  110. 0x0e8 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */
  111. 0x0ec (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */
  112. >;
  113. };
  114.  
  115. uart2_pins: pinmux_uart2_pins {
  116. pinctrl-single,pins = <
  117. 0x150 0x29 /* spi0_sclk.uart2_rxd_mux3, INPUT | MODE1 */
  118. 0x154 0x09 /* spi0_d0.uart2_txd_mux3, OUTPUT | MODE1 */
  119. 0x188 0x2a /* i2c0_sda.uart2_ctsn_mux0, INPUT | MODE2 */
  120. 0x18c 0x2a /* i2c0_scl.uart2_rtsn_mux0, INPUT | MODE2 */
  121. 0x030 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */
  122. 0x034 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */
  123. 0x038 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */
  124. 0x03c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */
  125. 0x1a0 (PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
  126. >;
  127. };
  128.  
  129. cpsw_default: cpsw_default {
  130. pinctrl-single,pins = <
  131. /* Slave 1 */
  132. 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
  133. 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */
  134. 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
  135. 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
  136. 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
  137. 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
  138. 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */
  139.  
  140.  
  141. /* Slave 2 */
  142. 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
  143. 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
  144. 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
  145. 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
  146. 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
  147. 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
  148. 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
  149. 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
  150. 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
  151. 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
  152. 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
  153. 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
  154. >;
  155. };
  156.  
  157. cpsw_sleep: cpsw_sleep {
  158. pinctrl-single,pins = <
  159. /* Slave 1 reset value */
  160. 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  161. 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  162. 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  163. 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  164. 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  165. 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  166. 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  167.  
  168. /* Slave 2 reset value*/
  169. 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  170. 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  171. 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  172. 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  173. 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  174. 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  175. 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  176. 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  177. 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  178. 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  179. 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  180. 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  181. >;
  182. };
  183.  
  184. davinci_mdio_default: davinci_mdio_default {
  185. pinctrl-single,pins = <
  186. /* MDIO */
  187. 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
  188. 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
  189. >;
  190. };
  191.  
  192. davinci_mdio_sleep: davinci_mdio_sleep {
  193. pinctrl-single,pins = <
  194. /* MDIO reset value */
  195. 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  196. 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  197. >;
  198. };
  199.  
  200. nandflash_pins_s0: nandflash_pins_s0 {
  201. pinctrl-single,pins = <
  202. 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
  203. 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
  204. 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
  205. 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
  206. 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
  207. 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
  208. 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
  209. 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
  210. 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
  211. 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
  212. 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
  213. 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
  214. 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
  215. 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
  216. 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
  217. >;
  218. };
  219. };
  220.  
  221. &elm {
  222. status = "okay";
  223. };
  224.  
  225. &gpmc {
  226. pinctrl-names = "default";
  227. pinctrl-0 = <&nandflash_pins_s0>;
  228. ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
  229. status = "okay";
  230.  
  231. nand@0,0 {
  232. reg = <0 0 0>; /* CS0, offset 0 */
  233. nand-bus-width = <8>;
  234. ti,nand-ecc-opt = "bch8";
  235. ti,nand-xfer-type = "polled";
  236.  
  237. gpmc,device-nand = "true";
  238. gpmc,device-width = <1>;
  239. gpmc,sync-clk-ps = <0>;
  240. gpmc,cs-on-ns = <0>;
  241. gpmc,cs-rd-off-ns = <44>;
  242. gpmc,cs-wr-off-ns = <44>;
  243. gpmc,adv-on-ns = <6>;
  244. gpmc,adv-rd-off-ns = <34>;
  245. gpmc,adv-wr-off-ns = <44>;
  246. gpmc,we-on-ns = <0>;
  247. gpmc,we-off-ns = <40>;
  248. gpmc,oe-on-ns = <0>;
  249. gpmc,oe-off-ns = <54>;
  250. gpmc,access-ns = <64>;
  251. gpmc,rd-cycle-ns = <82>;
  252. gpmc,wr-cycle-ns = <82>;
  253. gpmc,wait-on-read = "true";
  254. gpmc,wait-on-write = "true";
  255. gpmc,bus-turnaround-ns = <0>;
  256. gpmc,cycle2cycle-delay-ns = <0>;
  257. gpmc,clk-activation-ns = <0>;
  258. gpmc,wait-monitoring-ns = <0>;
  259. gpmc,wr-access-ns = <40>;
  260. gpmc,wr-data-mux-bus-ns = <0>;
  261.  
  262. #address-cells = <1>;
  263. #size-cells = <1>;
  264. elm_id = <&elm>;
  265. };
  266. };
  267.  
  268. &uart0 {
  269. pinctrl-names = "default";
  270. pinctrl-0 = <&uart0_pins>;
  271.  
  272. status = "okay";
  273. };
  274.  
  275. &uart1 {
  276. pinctrl-names = "default";
  277. pinctrl-0 = <&uart1_pins>;
  278. dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
  279. dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
  280. dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
  281. rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
  282. cts-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
  283. rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
  284.  
  285. /* No extra delay after/before transmissions */
  286. rs485-rts-delay = <0 0>;
  287.  
  288. /* Enable RS-485 */
  289. /*linux,rs485-enabled-at-boot-time;*/
  290.  
  291. status = "okay";
  292. };
  293.  
  294. &uart2 {
  295. pinctrl-names = "default";
  296. pinctrl-0 = <&uart2_pins>;
  297. dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
  298. dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
  299. dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
  300. rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  301.  
  302. status = "okay";
  303. };
  304.  
  305. &i2c1 {
  306. pinctrl-names = "default";
  307. pinctrl-0 = <&i2c1_pins>;
  308.  
  309. status = "okay";
  310. clock-frequency = <400000>;
  311.  
  312. tps: tps@2d {
  313. reg = <0x2d>;
  314. gpio-controller;
  315. #gpio-cells = <2>;
  316. interrupt-parent = <&gpio1>;
  317. interrupts = <28 GPIO_ACTIVE_LOW>;
  318. pinctrl-names = "default";
  319. pinctrl-0 = <&tps65910_pins>;
  320. };
  321.  
  322. at24@50 {
  323. compatible = "at24,24c02";
  324. pagesize = <8>;
  325. reg = <0x50>;
  326. };
  327.  
  328. tca6416: gpio@20 {
  329. compatible = "ti,tca6416";
  330. reg = <0x20>;
  331. gpio-controller;
  332. #gpio-cells = <2>;
  333. interrupt-parent = <&gpio0>;
  334. interrupts = <20 GPIO_ACTIVE_LOW>;
  335. pinctrl-names = "default";
  336. pinctrl-0 = <&tca6416_pins>;
  337. };
  338. };
  339.  
  340. &usb {
  341. status = "okay";
  342. };
  343.  
  344. &usb_ctrl_mod {
  345. status = "okay";
  346. };
  347.  
  348. &usb0_phy {
  349. status = "okay";
  350. };
  351.  
  352. &usb1_phy {
  353. status = "okay";
  354. };
  355.  
  356. &usb0 {
  357. status = "okay";
  358. dr_mode = "host";
  359. };
  360.  
  361. &usb1 {
  362. status = "okay";
  363. };
  364.  
  365. &cppi41dma {
  366. status = "okay";
  367. };
  368.  
  369. #include "tps65910.dtsi"
  370.  
  371. &tps {
  372. vcc1-supply = <&vbat>;
  373. vcc2-supply = <&vbat>;
  374. vcc3-supply = <&vbat>;
  375. vcc4-supply = <&vbat>;
  376. vcc5-supply = <&vbat>;
  377. vcc6-supply = <&vbat>;
  378. vcc7-supply = <&vbat>;
  379. vccio-supply = <&vbat>;
  380.  
  381. ti,en-ck32k-xtal = <1>;
  382.  
  383. regulators {
  384. vrtc_reg: regulator@0 {
  385. regulator-always-on;
  386. };
  387.  
  388. vio_reg: regulator@1 {
  389. regulator-always-on;
  390. };
  391.  
  392. vdd1_reg: regulator@2 {
  393. /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
  394. regulator-name = "vdd_mpu";
  395. regulator-min-microvolt = <912500>;
  396. regulator-max-microvolt = <1312500>;
  397. regulator-boot-on;
  398. regulator-always-on;
  399. };
  400.  
  401. vdd2_reg: regulator@3 {
  402. /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
  403. regulator-name = "vdd_core";
  404. regulator-min-microvolt = <912500>;
  405. regulator-max-microvolt = <1150000>;
  406. regulator-boot-on;
  407. regulator-always-on;
  408. };
  409.  
  410. vdd3_reg: regulator@4 {
  411. regulator-always-on;
  412. };
  413.  
  414. vdig1_reg: regulator@5 {
  415. regulator-always-on;
  416. };
  417.  
  418. vdig2_reg: regulator@6 {
  419. regulator-always-on;
  420. };
  421.  
  422. vpll_reg: regulator@7 {
  423. regulator-always-on;
  424. };
  425.  
  426. vdac_reg: regulator@8 {
  427. regulator-always-on;
  428. };
  429.  
  430. vaux1_reg: regulator@9 {
  431. regulator-always-on;
  432. };
  433.  
  434. vaux2_reg: regulator@10 {
  435. regulator-always-on;
  436. };
  437.  
  438. vaux33_reg: regulator@11 {
  439. regulator-always-on;
  440. };
  441.  
  442. vmmc_reg: regulator@12 {
  443. regulator-min-microvolt = <1800000>;
  444. regulator-max-microvolt = <3300000>;
  445. regulator-always-on;
  446. };
  447. };
  448. };
  449.  
  450. &mac {
  451. pinctrl-names = "default", "sleep";
  452. pinctrl-0 = <&cpsw_default>;
  453. pinctrl-1 = <&cpsw_sleep>;
  454. dual_emac = <1>;
  455. status = "okay";
  456. };
  457.  
  458. &davinci_mdio {
  459. pinctrl-names = "default", "sleep";
  460. pinctrl-0 = <&davinci_mdio_default>;
  461. pinctrl-1 = <&davinci_mdio_sleep>;
  462. status = "okay";
  463. };
  464.  
  465. &cpsw_emac0 {
  466. phy_id = <&davinci_mdio>, <0>;
  467. phy-mode = "rmii";
  468. dual_emac_res_vlan = <1>;
  469. };
  470.  
  471. &cpsw_emac1 {
  472. phy_id = <&davinci_mdio>, <7>;
  473. phy-mode = "rgmii-txid";
  474. dual_emac_res_vlan = <2>;
  475. };
  476.  
  477. &phy_sel {
  478. rmii-clock-ext = <1>;
  479. };
  480.  
  481. &mmc1 {
  482. vmmc-supply = <&vmmc_reg>;
  483. status = "okay";
  484. };
  485.  
  486. &mmc2 {
  487. status = "okay";
  488. vmmc-supply = <&wl12xx_vmmc>;
  489. ti,non-removable;
  490. bus-width = <4>;
  491. cap-power-off-card;
  492. pinctrl-names = "default";
  493. pinctrl-0 = <&mmc2_pins>;
  494. };
  495.  
  496. &sham {
  497. status = "okay";
  498. };
  499.  
  500. &aes {
  501. status = "okay";
  502. };
  503.  
  504. &gpio0 {
  505. ti,no-reset-on-init;
  506. };
  507.  
  508. &dcan1 {
  509. pinctrl-names = "default";
  510. pinctrl-0 = <&dcan1_pins>;
  511.  
  512. status = "okay";
  513. };
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