64DD MESS stuff

static UINT32 asic_data_reg = 0;

static UINT32 asic_status_reg = 0;
static UINT32 asic_command_reg = 0;

static UINT32 asic_bm_status_reg = 0;
static UINT32 asic_bm_ctl_reg = 0;

static UINT32 dd_interrupt = 0;

void signal_dd_interrupt(running_machine &machine, int interrupt)
{

    if (interrupt)
    {
        dd_interrupt |= interrupt;

        cputag_set_input_line(machine, "maincpu", INPUT_LINE_IRQ1, ASSERT_LINE);
    }
}

void clear_dd_interrupt(running_machine &machine, int interrupt)
{
    dd_interrupt &= ~interrupt;

    //if (!dd_interrupt)
    {
        cputag_set_input_line(machine, "maincpu", INPUT_LINE_IRQ1, CLEAR_LINE);
    }
}


READ32_HANDLER( n64_dd_reg_r )
{
    if (dd_interrupt) clear_dd_interrupt(space->machine(), 1);          // Clear the interrupt on every read (testing - OzOnE).

    switch (offset)
    {
        case 0x500/4:       // 64DD "ASIC_DATA" reg
            popmessage("64DD READ from DATA register, value == 0x%x", asic_data_reg);
            return asic_data_reg;
            break;

        case 0x508/4:       // 64DD "ASIC_STATUS" reg
            popmessage("64DD READ from STATUS register, value == 0x%x", asic_status_reg);
            return asic_status_reg;
            break;

        case 0x510/4:       // 64DD "ASIC_BM_STATUS" reg
            popmessage("64DD READ from BM_STATUS register, value == 0x%x", asic_bm_status_reg);
            return asic_bm_status_reg;
            break;

        default:
            popmessage("64DD Read - register 0x%x not defined!", offset*4);
            break;
    }

    return 0;
}

WRITE32_HANDLER( n64_dd_reg_w )
{
    switch (offset)
    {
        case 0x500/4:       // 64DD "ASIC_DATA" reg
            popmessage("64DD WRITE to DATA register, value == 0x%x", data);
            asic_data_reg = data;
            break;

        case 0x508/4:       // 64DD "ASIC_CMD" reg
            asic_command_reg = data;

            if (data == ASIC_READ_TIMER_MINUTE)
            {
                popmessage("64DD Command: 'ASIC_READ_TIMER_MINUTE'");
//              asic_data_reg = 0x04040404;                 // Write a dummy "minutes" value to data reg for now (OzOnE).
//              asic_status_reg = 0x00140007;
                signal_dd_interrupt(space->machine(), 1);   // Signal a 64DD interrupt on the R4300 INT1 pin (tell the ROM routine that data is ready).
            }
            else
                popmessage("64DD Command, value 0x%x", data);
            break;

        case 0x510/4:       // 64DD "ASIC_BM_CTL" reg
            if (data == BM_RESET)
                popmessage("64DD BM_CTL: 'BM_RESET'");
            else if (data == 0x00000000)
            {
                asic_bm_status_reg = 0x00000000;                // Clear the BM status word after reset (testing - OzOnE).
                asic_bm_ctl_reg = data;

                asic_status_reg = LEO_STAT_DISK;                // Shove in a disk (after BM reset is cleared), then...
                signal_dd_interrupt(space->machine(), 1);       // Trigger an interrupt to get ROM to read ASIC status.
                popmessage("64DD WRITE to BM_CTL register, value == 0x%x", data);
            }
            else
                popmessage("64DD WRITE to BM_CTL register, value == 0x%x", data);
            break;

        case 0x520/4:       // 64DD "HARD RESET" reg
            if (data == ASIC_RESET_CODE)
                popmessage("64DD HARD RESET");
            break;

        default:
            popmessage("64DD Write - register 0x%x not defined!", offset*4);
            break;
    }
}