library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity MPY8 is
		port(mpy : in std_logic; --set the clk and the multiply variable to the ones in std_logic
				a,b : in std_logic_vector(7 downto 0); -- a and b need to each be 8 bits
				rdy: out std_logic; --the output for MUL8 to signify it's finished multiplying
				prod: out std_logic_vector(15 downto 0)); --actual 16bit number (result)
end MPY8;

architecture Multiply of MPY8 is
		type state is (WT, S1, S2, S3, S4, S5, S6, S7);
		signal new_state : state; --need this signal to communicate with state transition process and asserted outputs.
		signal done : boolean;	 --when rdy is changed (when finished multiplying) in state transition process, change this and we will check in asserted outputs.
		signal clk	: std_logic;
	   	signal test1, test2, test3, test4, test5 : boolean;

	   	signal M_temp, NegM_temp	:	std_logic_vector(8 downto 0);
	   	signal P_temp	:	std_logic_vector(17 downto 0);
		begin
				--STATE TRANSITION PROCESS
				process is --define any local variables after this and before 'begin'
						variable curr_state : state := S7;


				begin
						if clk = '1' then --positive edge triggered clock
								case curr_state is
										when WT =>
												if mpy='1' then curr_state := S1;
												end if;
										when S1 =>
												if test1 then curr_state:= S6;
												elsif test2 then curr_state := S2;
												elsif test3 then curr_state := S3;
												elsif test4 then curr_state := S4;
												elsif test5 then curr_state := S5;
												end if;
										when S2 =>
												curr_state := S6;
										when S3 =>
												curr_state := S6;
										when S4 =>
												curr_state := S6;
										when S5 =>
												curr_state := S6;
										when S6 =>
												if done = false then curr_state := S1;
												elsif done = true then curr_state := S7;
												end if;
										when S7=>
												if mpy = '0' then curr_state := WT;
												end if;
								end case;
								new_state <= curr_state;
						end if;
						wait on clk;
				end process;




				-- Asserted Outputs process
				process is
				variable P : std_logic_vector(17 downto 0);
				variable M , NegM : std_logic_vector(8 downto 0);
				variable I : integer;
				variable rdy_val : std_logic;
				variable prod_val: std_logic_vector (15 downto 0);
				begin
					case new_state is
				 -- assigned output values go here
						when WT =>
							P(17 downto 9)		:= "000000000";
							P(8 downto 1)		:= a;
							P(0)				:= '0';
							M(7 downto 0)		:= b;
							M(8)				:= b(7);

							-- to get NegM
							NegM := (not M) + "000000001";		 -- this should work
							I := 0;
							prod_val := "ZZZZZZZZZZZZZZZZ";
							rdy_val := '0';			-- I think this might be a mistake. I think ready is supposed to be set to '0' here.

							--evaluate tests to be used

							test1		<=	( P(2 downto 0) = "000" ) or ( P(2 downto 0) = "111" );
							test2       <=	( P(2 downto 0) = "001" ) or ( P(2 downto 0) = "010" );
							test3       <=	( P(2 downto 0) = "011" );
							test4		<=	( P(2 downto 0) = "100" );
							test5		<=  ( P(2 downto 0) = "101" ) or ( P(2 downto 0) = "110" );

							M_temp <= M;
							NegM_temp <= NegM;
						when S1 =>
							I := I + 1;
							done	<=	not (I < 4);

						when S2 =>
							P(17 downto 9) := P(17 downto 9) & M(8 downto 0);

						when S3 =>
							P(17 downto 9) := P(17 downto 9) & (M(8 downto 0) sll 1);

						when S4 =>
							P(17 downto 9) := P(17 downto 9) & (NegM(8 downto 0) sll 1);

						when S5 =>
							P(17 downto 9) := P(17 downto 9) & NegM(8 downto 0);

						when S6 =>
							P := P sra 2;

						when S7 =>
							prod_val 	:= P(16 downto 1);
							rdy_val 	:= '1';

					end case;

					prod <= prod_val; -- deliver output values to signal
					rdy <= rdy_val;
					P_temp <= P;
					wait on new_state;
				end process;

				process is
				begin
	  				clk <= '0', '1' after 20 ns;
				  	wait for 40 ns;
				end process;

end Multiply;