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Prex 0.9.0 for the BeagleBoard with MMU and CACHE ON

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  1. diff -aburN prex-0.9.0/bsp/boot/arm/arch/elf_reloc.c prex-0.9.0-beagle/bsp/boot/arm/arch/elf_reloc.c
  2. --- prex-0.9.0/bsp/boot/arm/arch/elf_reloc.c    2009-10-01 12:09:22 +0000
  3. +++ prex-0.9.0-beagle/bsp/boot/arm/arch/elf_reloc.c 2010-08-05 10:53:42 +0000
  4. @@ -60,6 +60,9 @@
  5.         ELFDBG(("R_ARM_PC24: %lx -> %lx\n",
  6.             (long)where, (long)*where));
  7.         break;
  8. +   case R_ARM_V4BX:
  9. +       /* nothing to do: bx instruction is supported */
  10. +       break;
  11.     default:
  12.         ELFDBG(("Unkown relocation type=%d\n",
  13.             ELF32_R_TYPE(rel->r_info)));
  14. diff -aburN prex-0.9.0/bsp/boot/arm/arch/head.S prex-0.9.0-beagle/bsp/boot/arm/arch/head.S
  15. --- prex-0.9.0/bsp/boot/arm/arch/head.S 2009-10-01 12:06:10 +0000
  16. +++ prex-0.9.0-beagle/bsp/boot/arm/arch/head.S  2010-07-26 22:32:08 +0000
  17. @@ -47,7 +47,7 @@
  18.  
  19.     .align
  20.     .code 32
  21. -stack_end: .word   (BOOTSTKTOP - KERNBASE)
  22. +stack_end: .word   (BOOTSTKTOP - KERNOFFSET)
  23.  
  24.  start_vector:
  25.     mov r0, #0xd3       /* Enter SVC mode, Disable IRQ,FIQ */
  26. diff -aburN prex-0.9.0/bsp/boot/arm/beagle/Makefile.inc prex-0.9.0-beagle/bsp/boot/arm/beagle/Makefile.inc
  27. --- prex-0.9.0/bsp/boot/arm/beagle/Makefile.inc 1970-01-01 00:00:00 +0000
  28. +++ prex-0.9.0-beagle/bsp/boot/arm/beagle/Makefile.inc  2010-01-21 15:31:00 +0000
  29. @@ -0,0 +1,5 @@
  30. +
  31. +SRCS:=     arm/arch/head.S \
  32. +       arm/beagle/startup.c \
  33. +       arm/beagle/debug.c
  34. +
  35. diff -aburN prex-0.9.0/bsp/boot/arm/beagle/debug.c prex-0.9.0-beagle/bsp/boot/arm/beagle/debug.c
  36. --- prex-0.9.0/bsp/boot/arm/beagle/debug.c  1970-01-01 00:00:00 +0000
  37. +++ prex-0.9.0-beagle/bsp/boot/arm/beagle/debug.c   2010-01-21 15:31:00 +0000
  38. @@ -0,0 +1,97 @@
  39. +/*-
  40. + * Copyright (c) 2009, Richard Pandion
  41. + * All rights reserved.
  42. + *
  43. + * Redistribution and use in source and binary forms, with or without
  44. + * modification, are permitted provided that the following conditions
  45. + * are met:
  46. + * 1. Redistributions of source code must retain the above copyright
  47. + *    notice, this list of conditions and the following disclaimer.
  48. + * 2. Redistributions in binary form must reproduce the above copyright
  49. + *    notice, this list of conditions and the following disclaimer in the
  50. + *    documentation and/or other materials provided with the distribution.
  51. + * 3. Neither the name of the author nor the names of any co-contributors
  52. + *    may be used to endorse or promote products derived from this software
  53. + *    without specific prior written permission.
  54. + *
  55. + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  56. + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  57. + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  58. + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  59. + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  60. + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  61. + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  62. + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  63. + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  64. + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  65. + * SUCH DAMAGE.
  66. + */
  67. +
  68. +#include <sys/param.h>
  69. +#include <boot.h>
  70. +
  71. +#define L4_Per         0x49000000
  72. +#define L4_UART3       (L4_Per  + 0x20000)
  73. +#define UART_BASE      L4_UART3
  74. +#define UART_THR       (*(volatile uint32_t *)(UART_BASE + 0x00))
  75. +#define UART_DLL       (*(volatile uint32_t *)(UART_BASE + 0x00))
  76. +#define UART_IER       (*(volatile uint32_t *)(UART_BASE + 0x04))
  77. +#define UART_DLH       (*(volatile uint32_t *)(UART_BASE + 0x04))
  78. +#define UART_FCR       (*(volatile uint32_t *)(UART_BASE + 0x08))
  79. +#define UART_LCR       (*(volatile uint32_t *)(UART_BASE + 0x0C))
  80. +#define UART_MCR       (*(volatile uint32_t *)(UART_BASE + 0x10))
  81. +#define UART_LSR       (*(volatile uint32_t *)(UART_BASE + 0x14))
  82. +#define UART_MDR1      (*(volatile uint32_t *)(UART_BASE + 0x20))
  83. +
  84. +#define THRE       0x20
  85. +
  86. +#define UART_CLK       48000000
  87. +#define BAUD_RATE      115200
  88. +
  89. +#define MCR_DTR        0x01
  90. +#define MCR_RTS        0x02
  91. +#define LCR_8N1        0x03
  92. +#define LCR_BKSE       0x80                                /* Bank select enable        */
  93. +
  94. +#define FCR_FIFO_EN    0x01                                /* Fifo enable               */
  95. +#define FCR_RXSR       0x02                                /* Receiver soft reset       */
  96. +#define FCR_TXSR       0x04                                /* Transmitter soft reset    */
  97. +
  98. +#define LCRVAL     LCR_8N1                             /* 8 data, 1 stop, no parity */
  99. +#define MCRVAL     (MCR_DTR | MCR_RTS)                 /* RTS/DTR                   */
  100. +#define FCRVAL     (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs      */
  101. +
  102. +/*
  103. + * Print one chracter
  104. + */
  105. +void
  106. +debug_putc(int c)
  107. +{
  108. +
  109. +#if defined(DEBUG) && defined(CONFIG_DIAG_SERIAL)
  110. +   while ((UART_LSR & THRE) == 0) ;
  111. +   UART_THR = c;
  112. +#endif
  113. +}
  114. +
  115. +/*
  116. + * Initialize debug port.
  117. + */
  118. +void
  119. +debug_init(void)
  120. +{
  121. +
  122. +#if defined(DEBUG) && defined(CONFIG_DIAG_SERIAL)
  123. +   int baud_divisor = UART_CLK / 16 / BAUD_RATE;
  124. +
  125. +   UART_IER = 0x00;
  126. +   UART_MDR1 = 0x7;
  127. +   UART_LCR = LCR_BKSE | LCRVAL;
  128. +   UART_DLL = baud_divisor & 0xff;
  129. +   UART_DLH = (baud_divisor >> 8) & 0xff;
  130. +   UART_LCR = LCRVAL;
  131. +   UART_MCR = MCRVAL;
  132. +   UART_FCR = FCRVAL;
  133. +   UART_MDR1 = 0;
  134. +#endif
  135. +}
  136. diff -aburN prex-0.9.0/bsp/boot/arm/beagle/startup.c prex-0.9.0-beagle/bsp/boot/arm/beagle/startup.c
  137. --- prex-0.9.0/bsp/boot/arm/beagle/startup.c    1970-01-01 00:00:00 +0000
  138. +++ prex-0.9.0-beagle/bsp/boot/arm/beagle/startup.c 2010-01-21 15:31:00 +0000
  139. @@ -0,0 +1,89 @@
  140. +/*-
  141. + * Copyright (c) 2009, Richard Pandion
  142. + * All rights reserved.
  143. + *
  144. + * Redistribution and use in source and binary forms, with or without
  145. + * modification, are permitted provided that the following conditions
  146. + * are met:
  147. + * 1. Redistributions of source code must retain the above copyright
  148. + *    notice, this list of conditions and the following disclaimer.
  149. + * 2. Redistributions in binary form must reproduce the above copyright
  150. + *    notice, this list of conditions and the following disclaimer in the
  151. + *    documentation and/or other materials provided with the distribution.
  152. + * 3. Neither the name of the author nor the names of any co-contributors
  153. + *    may be used to endorse or promote products derived from this software
  154. + *    without specific prior written permission.
  155. + *
  156. + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  157. + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  158. + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  159. + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  160. + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  161. + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  162. + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  163. + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  164. + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  165. + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  166. + * SUCH DAMAGE.
  167. + */
  168. +
  169. +#include <sys/param.h>
  170. +#include <sys/bootinfo.h>
  171. +#include <boot.h>
  172. +
  173. +#define SDRC_BASE      0x6D000000
  174. +#define SDRC_MCFG_0    (*(volatile uint32_t *)(SDRC_BASE + 0x80))
  175. +#define SDRC_MCFG_1    (*(volatile uint32_t *)(SDRC_BASE + 0xB0))
  176. +
  177. +/*
  178. + * Setup boot information.
  179. + */
  180. +static void
  181. +bootinfo_init(void)
  182. +{
  183. +   struct bootinfo *bi = bootinfo;
  184. +  
  185. +   uint32_t size0 = 0, size1 = 0;
  186. +
  187. +   /*
  188. +    * Screen size
  189. +    */
  190. +   bi->video.text_x = 80;
  191. +   bi->video.text_y = 25;
  192. +
  193. +   /*
  194. +    * SDRAM - Autodetect
  195. +    * Should be 128 MB on RevA/B and 256MB on RevC
  196. +    */
  197. +
  198. +   size0 = SDRC_MCFG_0 >> 8;
  199. +   size0 &= 0x3FF; /* get bank size in 2-MB chunks */
  200. +   size0 *= 0x200000;  /* compute size */
  201. +   size1 = SDRC_MCFG_1 >> 8;
  202. +   size1 &= 0x3FF; /* get bank size in 2-MB chunks */
  203. +   size1 *= 0x200000;  /* compute size */
  204. +  
  205. +   bi->ram[0].base = 0x80000000;
  206. +   bi->ram[0].size = size0;
  207. +   bi->ram[0].type = MT_USABLE;
  208. +   if (size1 > 0) {
  209. +       /*
  210. +       * Normally, we are started from U-Boot and
  211. +       * it should have made memory banks contiguous...               
  212. +       */
  213. +       bi->ram[1].base = 0x80000000+size0;
  214. +       bi->ram[1].size = size1;
  215. +       bi->ram[1].type = MT_USABLE;
  216. +       bi->nr_rams = 2;
  217. +   } else {
  218. +       bi->nr_rams = 1;
  219. +   }
  220. +  
  221. +}
  222. +
  223. +void
  224. +startup(void)
  225. +{
  226. +
  227. +   bootinfo_init();
  228. +}
  229. diff -aburN prex-0.9.0/bsp/boot/common/elf.c prex-0.9.0-beagle/bsp/boot/common/elf.c
  230. --- prex-0.9.0/bsp/boot/common/elf.c    2009-07-28 13:45:20 +0000
  231. +++ prex-0.9.0-beagle/bsp/boot/common/elf.c 2010-08-05 10:56:14 +0000
  232. @@ -72,7 +72,8 @@
  233.  
  234.     if (nr_img == 0) {
  235.         /*  Initialize the load address */
  236. -       load_base = (vaddr_t)ptokv(phdr->p_paddr);
  237. +       /* load_base = (vaddr_t)ptokv(phdr->p_paddr); */
  238. +       load_base = (paddr_t)kvtop(phdr->p_vaddr);
  239.         if (load_base == 0) {
  240.             DPRINTF(("Invalid load address\n"));
  241.             return -1;
  242. @@ -185,7 +186,10 @@
  243.     for (i = 0; i < nr_reloc; i++) {
  244.         sym = &sym_table[ELF32_R_SYM(rela->r_info)];
  245.         ELFDBG(("%s\n", strtab + sym->st_name));
  246. -       if (sym->st_shndx != STN_UNDEF) {
  247. +       if (sym->st_info == 0) {
  248. +           /* Empty symbol used for R_ARM_V4BX, etc */
  249. +           sym_val = sym->st_value;
  250. +       } else if (sym->st_shndx != STN_UNDEF) {
  251.             sym_val = (Elf32_Addr)sect_addr[sym->st_shndx]
  252.                 + sym->st_value;
  253.             if (relocate_rela(rela, sym_val, target_sect) != 0)
  254. @@ -213,7 +217,10 @@
  255.     for (i = 0; i < nr_reloc; i++) {
  256.         sym = &sym_table[ELF32_R_SYM(rel->r_info)];
  257.         ELFDBG(("%s\n", strtab + sym->st_name));
  258. -       if (sym->st_shndx != STN_UNDEF) {
  259. +       if (sym->st_info == 0) {
  260. +           /* Empty symbol used for R_ARM_V4BX, etc */
  261. +           sym_val = sym->st_value;
  262. +       } else if (sym->st_shndx != STN_UNDEF) {
  263.             sym_val = (Elf32_Addr)sect_addr[sym->st_shndx]
  264.                 + sym->st_value;
  265.             if (relocate_rel(rel, sym_val, target_sect) != 0)
  266. diff -aburN prex-0.9.0/bsp/drv/dev/serial/Makefile.inc prex-0.9.0-beagle/bsp/drv/dev/serial/Makefile.inc
  267. --- prex-0.9.0/bsp/drv/dev/serial/Makefile.inc  2009-10-01 12:33:28 +0000
  268. +++ prex-0.9.0-beagle/bsp/drv/dev/serial/Makefile.inc   2010-01-21 15:31:00 +0000
  269. @@ -2,3 +2,4 @@
  270.  SRCS-$(CONFIG_SERIAL)+=        dev/serial/serial.c
  271.  SRCS-$(CONFIG_NS16550)+=   dev/serial/ns16550.c
  272.  SRCS-$(CONFIG_PL011)+=     dev/serial/pl011.c
  273. +SRCS-$(CONFIG_OMAP3_UART)+=        dev/serial/omap3_uart.c
  274. diff -aburN prex-0.9.0/bsp/drv/dev/serial/omap3_uart.c prex-0.9.0-beagle/bsp/drv/dev/serial/omap3_uart.c
  275. --- prex-0.9.0/bsp/drv/dev/serial/omap3_uart.c  1970-01-01 00:00:00 +0000
  276. +++ prex-0.9.0-beagle/bsp/drv/dev/serial/omap3_uart.c   2010-09-26 20:04:50 +0000
  277. @@ -0,0 +1,285 @@
  278. +/*-
  279. + * Copyright (c) 2009, Kohsuke Ohtani
  280. + * Copyright (c) 2009-2010, Richard Pandion
  281. + * All rights reserved.
  282. + *
  283. + * Redistribution and use in source and binary forms, with or without
  284. + * modification, are permitted provided that the following conditions
  285. + * are met:
  286. + * 1. Redistributions of source code must retain the above copyright
  287. + *    notice, this list of conditions and the following disclaimer.
  288. + * 2. Redistributions in binary form must reproduce the above copyright
  289. + *    notice, this list of conditions and the following disclaimer in the
  290. + *    documentation and/or other materials provided with the distribution.
  291. + * 3. Neither the name of the author nor the names of any co-contributors
  292. + *    may be used to endorse or promote products derived from this software
  293. + *    without specific prior written permission.
  294. + *
  295. + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  296. + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  297. + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  298. + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  299. + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  300. + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  301. + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  302. + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  303. + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  304. + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  305. + * SUCH DAMAGE.
  306. + */
  307. +
  308. +/*
  309. + * omap3_uart.c - OMAP3 integrated UART device driver
  310. + */
  311. +
  312. +#include <driver.h>
  313. +#include <tty.h>
  314. +#include <serial.h>
  315. +
  316. +/* #define DEBUG_OMAP3_UART 1 */
  317. +
  318. +#ifdef DEBUG_OMAP3_UART
  319. +#define DPRINTF(a) printf a
  320. +#else
  321. +#define DPRINTF(a)
  322. +#endif
  323. +
  324. +#define UART_BASE      CONFIG_OMAP3_UART_BASE
  325. +#define UART_IRQ       CONFIG_OMAP3_UART_IRQ
  326. +
  327. +#define UART_CLK       48000000
  328. +#define BAUD_RATE      115200
  329. +
  330. +#ifdef CONFIG_MMU
  331. +#define INTCPS_ILR(a)  (0xa8200100 + (0x04*a))
  332. +#else
  333. +#define INTCPS_ILR(a)  (0x48200100 + (0x04*a))
  334. +#endif
  335. +
  336. +/* Register offsets UART in OMAP35 SoC */
  337. +#define UART_RHR       (UART_BASE + 0x00)  /* receive buffer register */
  338. +#define UART_THR       (UART_BASE + 0x00)  /* transmit holding register */
  339. +#define UART_IER       (UART_BASE + 0x04)  /* interrupt enable register */
  340. +#define UART_FCR       (UART_BASE + 0x08)  /* FIFO control register */
  341. +#define UART_IIR       (UART_BASE + 0x08)  /* interrupt identification register */
  342. +#define UART_LCR       (UART_BASE + 0x0C)  /* line control register */
  343. +#define UART_MCR       (UART_BASE + 0x10)  /* modem control register */
  344. +#define UART_LSR       (UART_BASE + 0x14)  /* line status register */
  345. +#define UART_MSR       (UART_BASE + 0x18)  /* mode definition register */
  346. +#define UART_MDR1      (UART_BASE + 0x20)  /* modem status register */
  347. +#define UART_DLL       (UART_BASE + 0x00)  /* divisor latch LSB (LCR[7] = 1) */
  348. +#define UART_DLH       (UART_BASE + 0x04)  /* divisor latch MSB (LCR[7] = 1) */
  349. +
  350. +/* Interrupt enable register */
  351. +#define IER_RDA        0x01    /* enable receive data available */
  352. +#define IER_THRE       0x02    /* enable transmitter holding register empty */
  353. +#define IER_RLS        0x04    /* enable recieve line status */
  354. +#define IER_RMS        0x08    /* enable receive modem status */
  355. +
  356. +/* Interrupt identification register */
  357. +#define IIR_MSR        0x00    /* modem status change */
  358. +#define IIR_IP     0x01    /* 0 when interrupt pending */
  359. +#define IIR_TXB        0x02    /* transmitter holding register empty */
  360. +#define IIR_RXB        0x04    /* received data available */
  361. +#define IIR_LSR        0x06    /* line status change */
  362. +#define IIR_RXTO       0x0C  /* receive data timeout */
  363. +#define IIR_MASK       0x0E    /* mask off just the meaningful bits */
  364. +
  365. +/* line status register */
  366. +#define LSR_RCV_FIFO   0x80
  367. +#define LSR_TSRE       0x40    /* Transmitter empty: byte sent */
  368. +#define LSR_TXRDY      0x20    /* Transmitter buffer empty */
  369. +#define LSR_BI     0x10    /* Break detected */
  370. +#define LSR_FE     0x08    /* Framing error: bad stop bit */
  371. +#define LSR_PE     0x04    /* Parity error */
  372. +#define LSR_OE     0x02    /* Overrun, lost incoming byte */
  373. +#define LSR_RXRDY      0x01    /* Byte ready in Receive Buffer */
  374. +#define LSR_RCV_MASK   0x1f    /* Mask for incoming data or error */
  375. +
  376. +/* Bit definitions for line control */
  377. +#define LCR_BITS_MASK  0x03
  378. +#define LCR_STB2       0x04
  379. +#define LCR_PEN        0x08
  380. +#define LCR_EPS        0x10
  381. +#define LCR_SPS        0x20
  382. +#define LCR_BREAK      0x40
  383. +#define LCR_DLAB       0x80
  384. +
  385. +/* Bit definitions for modem control */
  386. +#define MCR_DTR        0x01
  387. +#define MCR_RTS        0x02
  388. +#define MCR_CDSTSCH    0x08
  389. +#define MCR_LOOPBACK   0x10
  390. +#define MCR_XON        0x20
  391. +#define MCR_TCRTLR 0x40
  392. +#define MCR_CLKSEL 0x80
  393. +
  394. +/* Bit definitions for fifo control register  */
  395. +#define FCR_ENABLE 0x01
  396. +#define FCR_RXCLR      0x02
  397. +#define FCR_TXCLR      0x04
  398. +#define FCR_DMA        0x08
  399. +
  400. +/* Mode settings for mode definition register 1  */
  401. +#define MDR1_ENABLE    0x00
  402. +#define MDR1_AUTOBAUD  0x02
  403. +#define MDR1_DISABLE   0x07
  404. +
  405. +/* Forward functions */
  406. +static void    omap3_uart_xmt_char(struct serial_port *, char);
  407. +static char    omap3_uart_rcv_char(struct serial_port *);
  408. +static void    omap3_uart_set_poll(struct serial_port *, int);
  409. +static int omap3_uart_isr(void *);
  410. +static void    omap3_uart_start(struct serial_port *);
  411. +static void    omap3_uart_stop(struct serial_port *);
  412. +static int omap3_uart_init(struct driver *);
  413. +
  414. +
  415. +struct driver omap3_uart_driver = {
  416. +   /* name */  "omap3_uart",
  417. +   /* devops */    NULL,
  418. +   /* devsz */ 0,
  419. +   /* flags */ 0,
  420. +   /* probe */ NULL,
  421. +   /* init */  omap3_uart_init,
  422. +   /* unload */    NULL,
  423. +};
  424. +
  425. +static struct serial_ops omap3_uart_ops = {
  426. +   /* xmt_char */  omap3_uart_xmt_char,
  427. +   /* rcv_char */  omap3_uart_rcv_char,
  428. +   /* set_poll */  omap3_uart_set_poll,
  429. +   /* start */ omap3_uart_start,
  430. +   /* stop */  omap3_uart_stop,
  431. +};
  432. +
  433. +
  434. +static struct serial_port omap3_uart_port;
  435. +
  436. +
  437. +static void
  438. +omap3_uart_xmt_char(struct serial_port *sp, char c)
  439. +{
  440. +   struct tty *tp = sp->tty;
  441. +   struct tty_queue *tq = &tp->t_outq;
  442. +
  443. +#define ttyq_empty(q)  ((q)->tq_count == 0)
  444. +
  445. +   while (!(bus_read_16(UART_LSR) & LSR_TXRDY))
  446. +       ;
  447. +   bus_write_16(UART_THR, (uint32_t)c);
  448. +
  449. +   if(ttyq_empty(tq))
  450. +       serial_xmt_done(sp);
  451. +  
  452. +}
  453. +
  454. +static char
  455. +omap3_uart_rcv_char(struct serial_port *sp)
  456. +{
  457. +   char c;
  458. +
  459. +  
  460. +   while (!(bus_read_16(UART_LSR) & LSR_RXRDY))
  461. +       ;
  462. +   c = bus_read_16(UART_RHR) & 0xff;
  463. +   return c;
  464. +}
  465. +
  466. +static void
  467. +omap3_uart_set_poll(struct serial_port *sp, int on)
  468. +{
  469. +
  470. +   if (on) {
  471. +       /* Disable interrupt for polling mode. */
  472. +       bus_write_16(UART_IER, 0x00);
  473. +   } else {
  474. +       /* enable interrupt again */
  475. +       bus_write_16(UART_IER, IER_RDA|IER_RLS);
  476. +   }
  477. +}
  478. +
  479. +static int
  480. +omap3_uart_isr(void *arg)
  481. +{
  482. +   struct serial_port *sp = arg;
  483. +   char c;
  484. +  
  485. +   switch ( bus_read_16(UART_IIR) & IIR_MASK) {
  486. +   case IIR_LSR:       /* Line status change */
  487. +       if( bus_read_16(UART_LSR) & (LSR_BI|LSR_FE|LSR_PE|LSR_OE) ) {
  488. +           /*
  489. +            * Status error
  490. +            * Read whatever happens to be in the buffer to "eat" the
  491. +            * spurious data associated with break, parity error, etc.
  492. +           */
  493. +           bus_read_16(UART_RHR);
  494. +       }
  495. +       /* Read LSR again to clear interrupt */
  496. +       bus_read_16(UART_LSR);
  497. +       break;
  498. +   case IIR_RXTO:      /* Receive data timeout */
  499. +           /*
  500. +            * "Eat" the spurious data (same as above).
  501. +            *  This also clears the interrupt.
  502. +           */
  503. +       bus_read_16(UART_RHR);
  504. +       break;
  505. +   case IIR_RXB:       /* Received data available */
  506. +       c = bus_read_16(UART_RHR) & 0xff; /* Read pending data */
  507. +       serial_rcv_char(sp, c);
  508. +       break;
  509. +   case IIR_TXB:       /* Transmitter holding register empty */
  510. +       bus_read_16(UART_IIR);      /* Clear interrupt */
  511. +       serial_xmt_done(sp);
  512. +       break;
  513. +   default:
  514. +       break;
  515. +   }
  516. +   return 0;
  517. +}
  518. +
  519. +static void
  520. +omap3_uart_start(struct serial_port *sp)
  521. +{
  522. +   int baud_divisor = UART_CLK / 16 / BAUD_RATE;
  523. +
  524. +   bus_write_16(UART_IER, 0x00);
  525. +   bus_write_16(UART_MDR1, MDR1_DISABLE);
  526. +   bus_write_16(UART_LCR, LCR_DLAB|LCR_BITS_MASK);
  527. +   bus_write_16(UART_DLL, baud_divisor & 0xff);
  528. +   bus_write_16(UART_DLH, (baud_divisor >> 8) & 0xff);
  529. +   bus_write_16(UART_LCR, LCR_BITS_MASK);
  530. +   bus_write_16(UART_MCR, MCR_DTR|MCR_RTS);
  531. +   bus_write_16(UART_FCR, FCR_RXCLR|FCR_TXCLR);
  532. +   bus_write_16(UART_MDR1, MDR1_ENABLE);
  533. +
  534. +   DPRINTF(("Installing UART IRQ\n"));
  535. +
  536. +   /* Install interrupt handler */
  537. +   sp->irq = irq_attach(UART_IRQ, IPL_COMM, 0, omap3_uart_isr,
  538. +                IST_NONE, sp);
  539. +
  540. +   /* Enable interrupts */
  541. +   bus_write_32(INTCPS_ILR(UART_IRQ), ((NIPLS-IPL_COMM)<<2));
  542. +   bus_write_16(UART_IER, IER_RDA|IER_RLS);
  543. +   DPRINTF(("UART interrupt enabled\n"));
  544. +}
  545. +
  546. +static void
  547. +omap3_uart_stop(struct serial_port *sp)
  548. +{
  549. +
  550. +   /* Disable interrupts */
  551. +   bus_write_16(UART_IER, 0x00);
  552. +   /* Disable UART */
  553. +   bus_write_16(UART_MDR1, MDR1_DISABLE);
  554. +}
  555. +
  556. +static int
  557. +omap3_uart_init(struct driver *self)
  558. +{
  559. +
  560. +   serial_attach(&omap3_uart_ops, &omap3_uart_port);
  561. +   return 0;
  562. +}
  563. diff -aburN prex-0.9.0/bsp/hal/arm/arch/cpufunc.S prex-0.9.0-beagle/bsp/hal/arm/arch/cpufunc.S
  564. --- prex-0.9.0/bsp/hal/arm/arch/cpufunc.S   2009-10-01 12:28:48 +0000
  565. +++ prex-0.9.0-beagle/bsp/hal/arm/arch/cpufunc.S    2010-09-26 19:15:28 +0000
  566. @@ -1,5 +1,6 @@
  567.  /*-
  568.   * Copyright (c) 2008, Kohsuke Ohtani
  569. + * Copyright (c) 2010, Richard Pandion
  570.   * All rights reserved.
  571.   *
  572.   * Redistribution and use in source and binary forms, with or without
  573. @@ -68,8 +69,9 @@
  574.   * Set TTB
  575.   */
  576.  ENTRY(set_ttb)
  577. +   mov r1,#0
  578.     mcr p15, 0, r0, c2, c0, 0   /* load new TTB */
  579. -   mcr p15, 0, r0, c8, c7, 0   /* invalidate I+D TLBs */
  580. +   mcr p15, 0, r1, c8, c7, 0   /* invalidate I+D TLBs */
  581.     nop
  582.     nop
  583.     nop
  584. @@ -79,11 +81,32 @@
  585.   * Switch TTB for context switch
  586.   */
  587.  ENTRY(switch_ttb)
  588. -   mcr p15, 0, r0, c7, c5, 0   /* flush I cache */
  589. -   mcr p15, 0, r0, c7, c6, 0   /* flush D cache */
  590. -   mcr p15, 0, r0, c7, c10, 4  /* drain the write buffer */
  591. -   mcr p15, 0, r0, c2, c0, 0   /* set the new TTB */
  592. -   mcr p15, 0, r0, c8, c7, 0   /* and flush the I+D tlbs */
  593. +#ifdef __beagle__
  594. +   mrc p15, 1, r1, c0, c0, 0   /* read CSIDR */
  595. +   ldr r2, =0x7fff
  596. +   ands    r2, r2, r1, lsr #13 /*  extract number of sets */
  597. +1:
  598. +   mov r1, #0                  /*  start with way #1 */
  599. +   orr r1, r1, r2, lsl #6      /*  set the set number */
  600. +   mcr p15, 0, r1, c7, c14, 2  /*  clean & invalidate by set/way */
  601. +   add r1, r1, #0x40000000     /*  then way #2 */
  602. +   mcr p15, 0, r1, c7, c14, 2  /*  clean & invalidate by set/way */
  603. +   add r1, r1, #0x40000000     /*  now way #3 */
  604. +   mcr p15, 0, r1, c7, c14, 2  /*  clean & invalidate by set/way */
  605. +   add r1, r1, #0x40000000     /*  end with way #4 */
  606. +   mcr p15, 0, r1, c7, c14, 2  /*  clean & invalidate by set/way */
  607. +   subs    r2, r2, #1          /*  decrement the set */
  608. +   bge 1b
  609. +   mov r1,#0
  610. +   mcr p15, 0, r1, c7, c5, 0   /* flush I cache */
  611. +#else
  612. +   mov r1,#0
  613. +   mcr p15, 0, r1, c7, c5, 0   /* flush I cache */
  614. +   mcr p15, 0, r1, c7, c6, 0   /* flush D cache */
  615. +#endif
  616. +   mcr p15, 0, r1, c7, c10, 4  /* drain the write buffer */
  617. +   mcr p15, 0, r0, c2, c0, 0   /* load new TTB */
  618. +   mcr p15, 0, r1, c8, c7, 0   /* invalidate I+D TLBs */
  619.     nop
  620.     nop
  621.     nop
  622. @@ -93,7 +116,11 @@
  623.   * Flush TLB
  624.   */
  625.  ENTRY(flush_tlb)
  626. -   mcr p15, 0, r0, c8, c7, 0   /* invalidate I+D TLBs */
  627. +   mov r1,#0
  628. +   mcr p15, 0, r1, c8, c7, 0   /* invalidate I+D TLBs */
  629. +   nop
  630. +   nop
  631. +   nop
  632.     mov pc, lr
  633.  
  634.  #endif /* !CONFIG_MMU */
  635. @@ -102,9 +129,30 @@
  636.   * Flush all cache
  637.   */
  638.  ENTRY(flush_cache)
  639. -   mcr p15, 0, r0, c7, c5, 0   /* flush I cache */
  640. -   mcr p15, 0, r0, c7, c6, 0   /* flush D cache */
  641. -   mcr p15, 0, r0, c7, c10, 4  /* drain write buffer */
  642. +#ifdef __beagle__
  643. +   mrc p15, 1, r1, c0, c0, 0   /* read CSIDR */
  644. +   ldr r2, =0x7fff
  645. +   ands    r2, r2, r1, lsr #13 /*  extract number of sets */
  646. +1:
  647. +   mov r1, #0                  /*  start with way #1 */
  648. +   orr r1, r1, r2, lsl #6      /*  set the set number */
  649. +   mcr p15, 0, r1, c7, c14, 2  /*  clean & invalidate by set/way */
  650. +   add r1, r1, #0x40000000     /*  then way #2 */
  651. +   mcr p15, 0, r1, c7, c14, 2  /*  clean & invalidate by set/way */
  652. +   add r1, r1, #0x40000000     /*  now way #3 */
  653. +   mcr p15, 0, r1, c7, c14, 2  /*  clean & invalidate by set/way */
  654. +   add r1, r1, #0x40000000     /*  end with way #4 */
  655. +   mcr p15, 0, r1, c7, c14, 2  /*  clean & invalidate by set/way */
  656. +   subs    r2, r2, #1          /*  decrement the set */
  657. +   bge 1b
  658. +   mov r1,#0
  659. +   mcr p15, 0, r1, c7, c5, 0   /* flush I cache */
  660. +#else
  661. +   mov r1,#0
  662. +   mcr p15, 0, r1, c7, c5, 0   /* flush I cache */
  663. +   mcr p15, 0, r1, c7, c6, 0   /* flush D cache */
  664. +#endif
  665. +   mcr p15, 0, r1, c7, c10, 4  /* drain write buffer */
  666.     mov pc, lr
  667.  
  668.     .end
  669. diff -aburN prex-0.9.0/bsp/hal/arm/arch/locore.S prex-0.9.0-beagle/bsp/hal/arm/arch/locore.S
  670. --- prex-0.9.0/bsp/hal/arm/arch/locore.S    2009-07-29 09:52:52 +0000
  671. +++ prex-0.9.0-beagle/bsp/hal/arm/arch/locore.S 2010-09-26 19:15:46 +0000
  672. @@ -1,5 +1,6 @@
  673.  /*-
  674.   * Copyright (c) 2005-2007, Kohsuke Ohtani
  675. + * Copyright (c) 2010, Richard Pandion
  676.   * All rights reserved.
  677.   *
  678.   * Redistribution and use in source and binary forms, with or without
  679. @@ -47,9 +48,7 @@
  680.   * Kernel start point
  681.   */
  682.  ENTRY(kernel_start)
  683. -#ifdef CONFIG_MMU
  684.     b   reset_entry     /* Relative jump */
  685. -#endif
  686.  vector_start:
  687.     /*
  688.      * Exception vector
  689. @@ -62,7 +61,7 @@
  690.     ldr pc, swi_target      /* 0x08 mode: svc */
  691.     ldr pc, prefetch_target /* 0x0c mode: abort */
  692.     ldr pc, abort_target    /* 0x10 mode: abort */
  693. -   nop             /* 0x14 reserved */
  694. +   ldr pc, unused_target   /* 0x14 unused */
  695.     ldr pc, irq_target      /* 0x18 mode: irq */
  696.     ldr pc, fiq_target      /* 0x1c mode: fiq */
  697.  
  698. @@ -71,6 +70,7 @@
  699.  swi_target:        .word   syscall_entry
  700.  prefetch_target:   .word   prefetch_entry
  701.  abort_target:      .word   abort_entry
  702. +unused_target:     .word   unused_entry
  703.  irq_target:        .word   interrupt_entry
  704.  fiq_target:        .word   fiq_entry
  705.  
  706. @@ -118,31 +118,50 @@
  707.  
  708.  #ifdef CONFIG_MMU
  709.     /*
  710. -    * Setup control register
  711. +    * Setup control register with default values
  712.      */
  713. -   mov r0, #CTL_DEFAULT
  714. +#ifdef __beagle__
  715. +   ldr r1, =(CTL_AFE | CTL_TRE | CTL_ICACHE | CTL_BPRD | CTL_CACHE | CTL_MMU)
  716. +   mrc p15, 0, r0, c1, c0, 0
  717. +   bic r0, r0, r1
  718.     mcr p15, 0, r0, c1, c0, 0
  719. +   /*
  720. +    * Disable L2 cache and set cache level to 0
  721. +    */
  722. +   mrc p15, 0, r0, c1, c0, 1       /* Read auxiliary control register */
  723. +   ldr r1,=(AUXCTL_L2EN)
  724. +   bic r0, r0, r1                  /* Disable L2 cache */
  725. +   mcr p15, 0, r0, c1, c0, 1       /* Load auxiliary control register... */
  726. +   mrc p15, 0, r0, c1, c0, 1       /* ...and read it back */
  727. +   ldr r0, =0x0
  728. +   mcr p15, 2, r0, c0, c0, 0       /* set cache level to 0 in CSSR */
  729. +#else
  730. +   ldr r0, =(CTL_32BP | CTL_32BD | CTL_LABT)
  731. +   mcr p15, 0, r0, c1, c0, 0
  732. +#endif
  733.  
  734.     /*
  735. -    * Initialize page table
  736. -    * The physical address 0-4M is mapped on virtual address 2G.
  737. +    * Initialize boot page directory
  738.      */
  739. -   mov r1, #BOOT_PGD_PHYS      /* Clear page directory */
  740. -   mov r2, #(BOOT_PGD_PHYS + 0x4000)   /* +16k */
  741. -   mov r0, #0
  742. +   ldr r1, =BOOT_PGD_PHYS      /* Page directory base address */
  743. +   add r2, r1, #0x4000         /* 16k in size */
  744. +   ldr r0, =0x0
  745.  1:
  746.     str r0, [r1], #4
  747.     teq r1, r2
  748.     bne 1b
  749.  
  750. -   mov r1, #(BOOT_PGD_PHYS + 0x2000) /* Set PTE0 address in pgd */
  751. -   mov r0, #BOOT_PTE0_PHYS /* WBUF/CACHE/SYSTEM attribute */
  752. -   orr r0, r0, #0x03
  753. -   str r0, [r1]
  754. -
  755. -   mov r1, #BOOT_PTE0_PHYS /* Fill boot page table entry */
  756. -   add r2, r1, #0x1000
  757. -   mov r0, #0x1e
  758. +   /*
  759. +    * Initialize boot page table entries for 4 sections of 1 MB each
  760. +    * (to map first 4 MB of RAM - see below)
  761. +    */
  762. +   ldr r1, =BOOT_PTE0_PHYS     /* Page table entry base address */
  763. +   add r2, r1, #0x1000         /* 4K in size (1k per section x 4 sections) */
  764. +#ifdef __beagle__
  765. +   ldr r0, =(RAMBASE | 0x1a)   /* We map from RAMBASE */
  766. +#else
  767. +   ldr r0, =(RAMBASE | 0x55a)  /* We map from RAMBASE */
  768. +#endif
  769.  1:
  770.     str r0, [r1], #4
  771.     add r0, r0, #0x1000
  772. @@ -150,44 +169,44 @@
  773.     bne 1b
  774.  
  775.     /*
  776. -    * Enable paging
  777. -    * The physical address 0-4M is temporarily mapped to virtial
  778. -    * address 0-4M. This is needed to enable paging.
  779. -    */
  780. -   mov r1, #BOOT_PGD_PHYS  /* Set PTE0 address in pgd */
  781. -   mov r0, #BOOT_PTE0_PHYS /* WBUF/CACHE/SYSTEM attribute */
  782. -   orr r0, r0, #0x03
  783. +    * Map first 4 MB of RAM on KERNBASE virtual address
  784. +    * Also map 1:1. This is required to enable paging
  785. +    */
  786. +   ldr r1, =(BOOT_PGD_PHYS + (KERNBASE >> 18))
  787. +   ldr r2, =(BOOT_PGD_PHYS + (RAMBASE  >> 18))
  788. +   ldr r0, =(BOOT_PTE0_PHYS | 0x01)
  789. +   str r0, [r1], #4
  790. +   str r0, [r2], #4
  791. +   add r0, r0, #0x400
  792. +   str r0, [r1], #4
  793. +   str r0, [r2], #4
  794. +   add r0, r0, #0x400
  795. +   str r0, [r1], #4
  796. +   str r0, [r2], #4
  797. +   add r0, r0, #0x400
  798.     str r0, [r1]
  799. +   str r0, [r2], #4
  800.  
  801. -   mov r0, #0
  802. -   mcr p15, 0, r0, c7, c10, 4  /* drain write buffer */
  803. -   mcr p15, 0, r0, c8, c7, 0   /* flush I,D TLBs */
  804. -   mov r1, #BOOT_PGD_PHYS
  805. -   mcr p15, 0, r1, c2, c0, 0   /* load page table pointer */
  806. -   mov r0, #-1
  807. -   mcr p15, 0, r0, c3, c0  /* load domain access register */
  808. -   mrc p15, 0, r0, c1, c0, 0
  809. -   orr r0, r0, #0x1000     /* I-cache enable */
  810. -   orr r0, r0, #0x003d     /* Write buffer, mmu */
  811. -   mcr p15, 0, r0, c1, c0, 0
  812. +   mcr p15, 0, r0, c7, c10, 4      /* Drain the write buffer */
  813. +   ldr r1, =BOOT_PGD_PHYS
  814. +   mcr p15, 0, r1, c2, c0, 0       /* Load page table pointer */
  815. +   mcr p15, 0, r0, c8, c7, 0       /* Flush I,D TLBs */
  816. +   ldr r0, =0x55555555             /* AP is defined in page table entries */
  817. +   mcr p15, 0, r0, c3, c0          /* Load domain access register */
  818. +   mrc p15, 0, r0, c1, c0, 0       /* Read control register */
  819. +   ldr r1, =(CTL_ICACHE | CTL_BPRD | CTL_CACHE | CTL_MMU)
  820. +   orr r0, r0, r1                  /* Enable MMU, caches and branch prediction */
  821. +   ldr r1, =(CTL_AFLT)
  822. +   bic r0, r0, r1                  /* Disable alignment checks */
  823. +   mcr p15, 0, r0, c1, c0, 0       /* Load control register... */
  824. +   mrc p15, 0, r0, c1, c0, 0       /* ...and read it back */
  825.  
  826.     /*
  827. -    * Reload PC register for virutal address.
  828. +    * Reload PC register for virtual address.
  829.      */
  830.     ldr pc, reload_pc_target    /* Reset pc here */
  831.  reload_pc:
  832.  
  833. -   /*
  834. -    * Unmap 0-4M.
  835. -    * Since the first page must be accessible for exception
  836. -    * vector, we have to map it later.
  837. -    */
  838. -   mov r1, #BOOT_PGD_PHYS  /* Set PTE0 address in pgd */
  839. -   add r1, r1, #KERNBASE
  840. -   mov r0, #0
  841. -   str r0, [r1]
  842. -   mcr p15, 0, r0, c8, c7, 0   /* flush I,D TLBs */
  843. -
  844.  #endif /* !CONFIG_MMU */
  845.  
  846.     /*
  847. @@ -418,6 +437,9 @@
  848.     nop             /* Instruction gap for ldm^ */
  849.     movs    pc, lr          /* Exit, with restoring cpsr */
  850.  
  851. +ENTRY(unused_entry)
  852. +   b   unused_entry        /* Not support... */
  853. +  
  854.  ENTRY(fiq_entry)
  855.     b   fiq_entry       /* Not support... */
  856.  
  857. diff -aburN prex-0.9.0/bsp/hal/arm/arch/mmu.c prex-0.9.0-beagle/bsp/hal/arm/arch/mmu.c
  858. --- prex-0.9.0/bsp/hal/arm/arch/mmu.c   2009-10-01 12:28:56 +0000
  859. +++ prex-0.9.0-beagle/bsp/hal/arm/arch/mmu.c    2010-09-27 05:51:24 +0000
  860. @@ -1,5 +1,6 @@
  861.  /*-
  862.   * Copyright (c) 2008-2009, Kohsuke Ohtani
  863. + * Copyright (c) 2010, Richard Pandion
  864.   * All rights reserved.
  865.   *
  866.   * Redistribution and use in source and binary forms, with or without
  867. @@ -126,19 +127,16 @@
  868.         pte_flag = 0;
  869.         break;
  870.     case PG_READ:
  871. -       pte_flag = (uint32_t)(PTE_PRESENT | PTE_WBUF | PTE_CACHE |
  872. -                     PTE_USER_RO);
  873. +       pte_flag = (uint32_t)(PTE_PRESENT | PTE_CACHE | PTE_USER_RO);
  874.         break;
  875.     case PG_WRITE:
  876. -       pte_flag = (uint32_t)(PTE_PRESENT | PTE_WBUF | PTE_CACHE |
  877. -                     PTE_USER_RW);
  878. +       pte_flag = (uint32_t)(PTE_PRESENT | PTE_CACHE | PTE_USER_RW);
  879.         break;
  880.     case PG_SYSTEM:
  881. -       pte_flag = (uint32_t)(PTE_PRESENT | PTE_WBUF | PTE_CACHE |
  882. -                     PTE_SYSTEM);
  883. +       pte_flag = (uint32_t)(PTE_PRESENT | PTE_CACHE | PTE_SYSTEM);
  884.         break;
  885.     case PG_IOMEM:
  886. -       pte_flag = (uint32_t)(PTE_PRESENT | PTE_SYSTEM);
  887. +       pte_flag = (uint32_t)(PTE_PRESENT | PTE_WBUF  | PTE_SYSTEM);
  888.         break;
  889.     default:
  890.         panic("mmu_map");
  891. @@ -199,7 +197,7 @@
  892.     memcpy(&pgd[i], &boot_pgd[i], (size_t)(L1TBL_SIZE - i * 4));
  893.  
  894.     /* Map vector page (address 0) */
  895. -   mmu_map(pgd, 0, 0, PAGE_SIZE, PG_SYSTEM);
  896. +   mmu_map(pgd, CONFIG_RAM_BASE, CONFIG_ARM_VECTORS, PAGE_SIZE, PG_SYSTEM);
  897.     return pgd;
  898.  }
  899.  
  900. @@ -278,10 +276,14 @@
  901.  mmu_premap(paddr_t phys, vaddr_t virt)
  902.  {
  903.     pte_t pte = (pte_t)BOOT_PTE1;
  904. +   int pte_index;
  905.  
  906. -   memset(pte, 0, L2TBL_SIZE);
  907.     boot_pgd[PAGE_DIR(virt)] = (uint32_t)kvtop(pte) | PDE_PRESENT;
  908. -   pte[PAGE_TABLE(virt)] = (uint32_t)phys | PTE_PRESENT | PTE_SYSTEM;
  909. +   for (pte_index = 0; pte_index < L2TBL_SIZE ; pte_index++) {
  910. +       pte[pte_index] = (uint32_t)phys | PTE_PRESENT | PTE_WBUF | PTE_SYSTEM;
  911. +       phys += 0x1000;
  912. +   }
  913. +
  914.     flush_tlb();
  915.  }
  916.  
  917. @@ -320,6 +322,6 @@
  918.     /*
  919.      * Map vector page.
  920.      */
  921. -   if (mmu_map(boot_pgd, 0, CONFIG_ARM_VECTORS, PAGE_SIZE, PG_SYSTEM))
  922. +   if (mmu_map(boot_pgd, CONFIG_RAM_BASE, CONFIG_ARM_VECTORS, PAGE_SIZE, PG_SYSTEM))
  923.         panic("mmu_init");
  924.  }
  925. diff -aburN prex-0.9.0/bsp/hal/arm/beagle/Makefile.inc prex-0.9.0-beagle/bsp/hal/arm/beagle/Makefile.inc
  926. --- prex-0.9.0/bsp/hal/arm/beagle/Makefile.inc  1970-01-01 00:00:00 +0000
  927. +++ prex-0.9.0-beagle/bsp/hal/arm/beagle/Makefile.inc   2010-07-07 23:02:06 +0000
  928. @@ -0,0 +1,17 @@
  929. +
  930. +SRCS:=     arm/arch/locore.S \
  931. +       arm/beagle/locore_beagle.S \
  932. +       arm/arch/cpufunc.S \
  933. +       arm/arch/cpu.c \
  934. +       arm/arch/trap.c \
  935. +       arm/arch/context.c \
  936. +       arm/beagle/interrupt.c \
  937. +       arm/beagle/clock.c \
  938. +       arm/beagle/machdep.c
  939. +
  940. +ifeq ($(CONFIG_MMU),y)
  941. +SRCS+=     arm/arch/mmu.c
  942. +endif
  943. +ifeq ($(DEBUG),1)
  944. +SRCS+=     arm/beagle/diag.c
  945. +endif
  946. diff -aburN prex-0.9.0/bsp/hal/arm/beagle/clock.c prex-0.9.0-beagle/bsp/hal/arm/beagle/clock.c
  947. --- prex-0.9.0/bsp/hal/arm/beagle/clock.c   1970-01-01 00:00:00 +0000
  948. +++ prex-0.9.0-beagle/bsp/hal/arm/beagle/clock.c    2010-09-26 19:16:36 +0000
  949. @@ -0,0 +1,127 @@
  950. +/*-
  951. + * Copyright (c) 2009-2010, Richard Pandion
  952. + * All rights reserved.
  953. + *
  954. + * Redistribution and use in source and binary forms, with or without
  955. + * modification, are permitted provided that the following conditions
  956. + * are met:
  957. + * 1. Redistributions of source code must retain the above copyright
  958. + *    notice, this list of conditions and the following disclaimer.
  959. + * 2. Redistributions in binary form must reproduce the above copyright
  960. + *    notice, this list of conditions and the following disclaimer in the
  961. + *    documentation and/or other materials provided with the distribution.
  962. + * 3. Neither the name of the author nor the names of any co-contributors
  963. + *    may be used to endorse or promote products derived from this software
  964. + *    without specific prior written permission.
  965. + *
  966. + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  967. + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  968. + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  969. + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  970. + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  971. + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  972. + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  973. + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  974. + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  975. + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  976. + * SUCH DAMAGE.
  977. + */
  978. +
  979. +/*
  980. + * clock.c - clock driver
  981. + */
  982. +
  983. +#include <kernel.h>
  984. +#include <timer.h>
  985. +#include <irq.h>
  986. +#include <cpufunc.h>
  987. +#include <sys/ipl.h>
  988. +
  989. +#include "platform.h"
  990. +
  991. +/* Interrupt vector for timer (GPTIMER2) */
  992. +#define CLOCK_IRQ  38
  993. +
  994. +/* The clock rate per second - 32Khz */
  995. +/* We are using the 32 Khz clock in order to get accurate 1 ms tick rate */
  996. +#define CLOCK_RATE 32768L
  997. +
  998. +/* The initial counter value */
  999. +#define TIMER_COUNT    (CLOCK_RATE / HZ)
  1000. +
  1001. +/* PRCM registers for timer */
  1002. +#define CM_FCLKEN_PER  (*(volatile uint32_t *)(PER_CM_BASE + 0x00))
  1003. +#define CM_ICLKEN_PER  (*(volatile uint32_t *)(PER_CM_BASE + 0x10))
  1004. +#define CM_CLKSEL_PER  (*(volatile uint32_t *)(PER_CM_BASE + 0x40))
  1005. +
  1006. +/* Timer 2 registers (32 bit regs) */
  1007. +#define TIDR           (*(volatile uint32_t *)(TIMER_BASE + 0x00)) /* r */
  1008. +#define TIOCP_CFG      (*(volatile uint32_t *)(TIMER_BASE + 0x10)) /* rw */
  1009. +#define TISTAT         (*(volatile uint32_t *)(TIMER_BASE + 0x14)) /* r */
  1010. +#define TISR           (*(volatile uint32_t *)(TIMER_BASE + 0x18)) /* rw */
  1011. +#define TIER           (*(volatile uint32_t *)(TIMER_BASE + 0x1C)) /* rw */
  1012. +#define TWER           (*(volatile uint32_t *)(TIMER_BASE + 0x20)) /* rw */
  1013. +#define TCLR           (*(volatile uint32_t *)(TIMER_BASE + 0x24)) /* rw */
  1014. +#define TCRR           (*(volatile uint32_t *)(TIMER_BASE + 0x28)) /* rw */
  1015. +#define TLDR           (*(volatile uint32_t *)(TIMER_BASE + 0x2C)) /* rw */
  1016. +#define TTGR           (*(volatile uint32_t *)(TIMER_BASE + 0x30)) /* rw */
  1017. +#define TWPS           (*(volatile uint32_t *)(TIMER_BASE + 0x34)) /* r */
  1018. +#define TMAR           (*(volatile uint32_t *)(TIMER_BASE + 0x38)) /* rw */
  1019. +#define TCAR1          (*(volatile uint32_t *)(TIMER_BASE + 0x3c)) /* r */
  1020. +#define TSICR          (*(volatile uint32_t *)(TIMER_BASE + 0x40)) /* rw */
  1021. +#define TCAR2          (*(volatile uint32_t *)(TIMER_BASE + 0x44)) /* r */
  1022. +#define TPIR           (*(volatile uint32_t *)(TIMER_BASE + 0x48)) /* rw */
  1023. +#define TNIR           (*(volatile uint32_t *)(TIMER_BASE + 0x4C)) /* rw */
  1024. +
  1025. +#define INTCPS_ILR(a)  (*(volatile uint32_t *)(MPU_INTC_BASE + 0x100 + (0x04*a)))
  1026. +
  1027. +/*
  1028. + * Clock interrupt service routine.
  1029. + * No H/W reprogram is required.
  1030. + */
  1031. +static int
  1032. +clock_isr(void *arg)
  1033. +{
  1034. +
  1035. +   splhigh();
  1036. +   timer_handler();
  1037. +   TISR = 0x02;    /* Clear GPT2 interrupt pending flag */
  1038. +   spl0();
  1039. +
  1040. +   return INT_DONE;
  1041. +}
  1042. +
  1043. +/*
  1044. + * Initialize clock H/W chip.
  1045. + * Setup clock tick rate and install clock ISR.
  1046. + */
  1047. +void
  1048. +clock_init(void)
  1049. +{
  1050. +   irq_t clock_irq;
  1051. +
  1052. +   /* Setup PRCM so that GPT2 uses 32Khz clock now */
  1053. +   CM_CLKSEL_PER &= 0xFE;  /* GPT2 clock = 32K_FCLK */
  1054. +   CM_ICLKEN_PER |= 0x10;  /* Enable Interface clock on GPT2 */
  1055. +   CM_FCLKEN_PER |= 0x10;  /* Enable Functional clock on GPT2 */
  1056. +
  1057. +   TIOCP_CFG = 0x02;   /* Now, reset GPT2 */
  1058. +   while (TISTAT != 0x01) ;
  1059. +
  1060. +   TCLR &= 0xFFFFFF00; /* Stop GPT2 and disable all timing modes */
  1061. +   TPIR = 232000;      /* Positive increment value for accurate 1 ms tick */
  1062. +   TNIR = -768000;     /* Negative increment value for accurate 1 ms tick */
  1063. +   TLDR = 0xFFFFFFE0;  /* Load value for 1 ms tick */
  1064. +   TCRR = 0xFFFFFFE0;  /* Current value = Load value */
  1065. +
  1066. +   /* Install ISR */
  1067. +   clock_irq = irq_attach(CLOCK_IRQ, IPL_CLOCK, 0, clock_isr,
  1068. +                  IST_NONE, NULL);
  1069. +
  1070. +   /* Enable overflow interrupt in auto-reload mode */
  1071. +   INTCPS_ILR(CLOCK_IRQ) = ((NIPLS-IPL_CLOCK)<<2);
  1072. +   TIER = 0x02;        /* Enable overflow interrupt */
  1073. +   TCLR |= 0x03;       /* Start timer in auto-reload mode */
  1074. +
  1075. +   DPRINTF(("Clock rate: %d ticks/sec\n", CONFIG_HZ));
  1076. +}
  1077. diff -aburN prex-0.9.0/bsp/hal/arm/beagle/diag.c prex-0.9.0-beagle/bsp/hal/arm/beagle/diag.c
  1078. --- prex-0.9.0/bsp/hal/arm/beagle/diag.c    1970-01-01 00:00:00 +0000
  1079. +++ prex-0.9.0-beagle/bsp/hal/arm/beagle/diag.c 2010-09-26 19:16:46 +0000
  1080. @@ -0,0 +1,75 @@
  1081. +/*-
  1082. + * Copyright (c) 2009-2010, Richard Pandion
  1083. + * All rights reserved.
  1084. + *
  1085. + * Redistribution and use in source and binary forms, with or without
  1086. + * modification, are permitted provided that the following conditions
  1087. + * are met:
  1088. + * 1. Redistributions of source code must retain the above copyright
  1089. + *    notice, this list of conditions and the following disclaimer.
  1090. + * 2. Redistributions in binary form must reproduce the above copyright
  1091. + *    notice, this list of conditions and the following disclaimer in the
  1092. + *    documentation and/or other materials provided with the distribution.
  1093. + * 3. Neither the name of the author nor the names of any co-contributors
  1094. + *    may be used to endorse or promote products derived from this software
  1095. + *    without specific prior written permission.
  1096. + *
  1097. + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  1098. + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  1099. + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  1100. + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  1101. + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  1102. + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  1103. + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  1104. + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  1105. + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  1106. + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  1107. + * SUCH DAMAGE.
  1108. + */
  1109. +
  1110. +/*
  1111. + * diag.c - diagnostic message support
  1112. + */
  1113. +
  1114. +#include <sys/bootinfo.h>
  1115. +#include <kernel.h>
  1116. +#include <cpufunc.h>
  1117. +
  1118. +#include "platform.h"
  1119. +
  1120. +#define UART_THR   (*(volatile uint32_t *)(UART_BASE + 0x00))
  1121. +#define UART_LSR   (*(volatile uint32_t *)(UART_BASE + 0x14))
  1122. +
  1123. +/* Flag register */
  1124. +#define THRE   0x20    /* Transmit FIFO full */
  1125. +
  1126. +static void
  1127. +serial_putc(int c)
  1128. +{
  1129. +
  1130. +   while ((UART_LSR & THRE) == 0) ;
  1131. +   UART_THR = (uint32_t)c;
  1132. +}
  1133. +
  1134. +void
  1135. +diag_puts(char *buf)
  1136. +{
  1137. +
  1138. +   while (*buf) {
  1139. +       if (*buf == '\n')
  1140. +           serial_putc('\r');
  1141. +       serial_putc(*buf++);
  1142. +   }
  1143. +}
  1144. +
  1145. +/*
  1146. + * Init
  1147. + */
  1148. +void
  1149. +diag_init(void)
  1150. +{
  1151. +
  1152. +#ifdef CONFIG_MMU
  1153. +   mmu_premap(0x49000000, L4_Per);
  1154. +#endif
  1155. +}
  1156. diff -aburN prex-0.9.0/bsp/hal/arm/beagle/interrupt.c prex-0.9.0-beagle/bsp/hal/arm/beagle/interrupt.c
  1157. --- prex-0.9.0/bsp/hal/arm/beagle/interrupt.c   1970-01-01 00:00:00 +0000
  1158. +++ prex-0.9.0-beagle/bsp/hal/arm/beagle/interrupt.c    2010-09-26 19:16:54 +0000
  1159. @@ -0,0 +1,216 @@
  1160. +/*-
  1161. + * Copyright (c) 2009-2010, Richard Pandion
  1162. + * All rights reserved.
  1163. + *
  1164. + * Redistribution and use in source and binary forms, with or without
  1165. + * modification, are permitted provided that the following conditions
  1166. + * are met:
  1167. + * 1. Redistributions of source code must retain the above copyright
  1168. + *    notice, this list of conditions and the following disclaimer.
  1169. + * 2. Redistributions in binary form must reproduce the above copyright
  1170. + *    notice, this list of conditions and the following disclaimer in the
  1171. + *    documentation and/or other materials provided with the distribution.
  1172. + * 3. Neither the name of the author nor the names of any co-contributors
  1173. + *    may be used to endorse or promote products derived from this software
  1174. + *    without specific prior written permission.
  1175. + *
  1176. + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  1177. + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  1178. + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  1179. + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  1180. + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  1181. + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  1182. + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  1183. + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  1184. + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  1185. + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  1186. + * SUCH DAMAGE.
  1187. + */
  1188. +
  1189. +/*
  1190. + * interrupt.c - interrupt handling routines
  1191. + */
  1192. +
  1193. +#include <sys/ipl.h>
  1194. +#include <kernel.h>
  1195. +#include <hal.h>
  1196. +#include <irq.h>
  1197. +#include <cpufunc.h>
  1198. +#include <context.h>
  1199. +#include <locore.h>
  1200. +
  1201. +#include "platform.h"
  1202. +
  1203. +/* MPU INTC Registers */
  1204. +#define INTCPS_SYSCONFIG       (*(volatile uint32_t *)(MPU_INTC_BASE + 0x010))
  1205. +#define INTCPS_SYSSTATUS       (*(volatile uint32_t *)(MPU_INTC_BASE + 0x014))
  1206. +#define INTCPS_SIR_IRQ         (*(volatile uint32_t *)(MPU_INTC_BASE + 0x040))
  1207. +#define INTCPS_SIR_FIQ         (*(volatile uint32_t *)(MPU_INTC_BASE + 0x044))
  1208. +#define INTCPS_CONTROL         (*(volatile uint32_t *)(MPU_INTC_BASE + 0x048))
  1209. +#define INTCPS_PROTECTION      (*(volatile uint32_t *)(MPU_INTC_BASE + 0x04C))
  1210. +#define INTCPS_IDLE                (*(volatile uint32_t *)(MPU_INTC_BASE + 0x050))
  1211. +#define INTCPS_IRQ_PRIORITY        (*(volatile uint32_t *)(MPU_INTC_BASE + 0x060))
  1212. +#define INTCPS_FIQ_PRIORITY        (*(volatile uint32_t *)(MPU_INTC_BASE + 0x064))
  1213. +#define INTCPS_THRESHOLD       (*(volatile uint32_t *)(MPU_INTC_BASE + 0x068))
  1214. +#define INTCPS_ITR(a)          (*(volatile uint32_t *)(MPU_INTC_BASE + 0x080 + (0x20*a)))
  1215. +#define INTCPS_MIR(a)          (*(volatile uint32_t *)(MPU_INTC_BASE + 0x084 + (0x20*a)))
  1216. +#define INTCPS_MIR_CLEAR(a)        (*(volatile uint32_t *)(MPU_INTC_BASE + 0x088 + (0x20*a)))
  1217. +#define INTCPS_MIR_SET(a)      (*(volatile uint32_t *)(MPU_INTC_BASE + 0x08C + (0x20*a)))
  1218. +#define INTCPS_ISR_SET(a)      (*(volatile uint32_t *)(MPU_INTC_BASE + 0x090 + (0x20*a)))
  1219. +#define INTCPS_ISR_CLEAR(a)        (*(volatile uint32_t *)(MPU_INTC_BASE + 0x094 + (0x20*a)))
  1220. +#define INTCPS_PENDING_IRQ(a)  (*(volatile uint32_t *)(MPU_INTC_BASE + 0x098 + (0x20*a)))
  1221. +#define INTCPS_PENDING_FIQ(a)  (*(volatile uint32_t *)(MPU_INTC_BASE + 0x09C + (0x20*a)))
  1222. +
  1223. +
  1224. +/*
  1225. + * Interrupt Priority Level
  1226. + *
  1227. + * Each interrupt has its logical priority level, with 0 being
  1228. + * the lowest priority. While some ISR is running, all lower
  1229. + * priority interrupts are masked off.
  1230. + */
  1231. +volatile int irq_level;
  1232. +
  1233. +/*
  1234. + * Interrupt mapping table. As the number of interrupts on the
  1235. + * Beagle is > 32, we need a 2 dimensions array for the mask table
  1236. + */
  1237. +static int ipl_table[NIRQS];           /* vector -> level */
  1238. +static uint32_t mask_table[NIPLS][NIRQS>>5];   /* level -> mask   */
  1239. +
  1240. +/*
  1241. + * Set mask for current ipl
  1242. + */
  1243. +static void
  1244. +update_mask(void)
  1245. +{
  1246. +   int i;
  1247. +   uint32_t mask;
  1248. +
  1249. +   for (i = 0; i < (NIRQS>>5); i++) {
  1250. +       mask = mask_table[irq_level][i];
  1251. +       INTCPS_MIR(i) = ~mask;
  1252. +   }
  1253. +}
  1254. +
  1255. +/*
  1256. + * Unmask interrupt in INTC for specified irq.
  1257. + * The interrupt mask table is also updated.
  1258. + * Assumes CPU interrupt is disabled in caller.
  1259. + */
  1260. +void
  1261. +interrupt_unmask(int vector, int level)
  1262. +{
  1263. +   int i;
  1264. +   uint32_t unmask = (uint32_t)1 << (vector & 0x1f);
  1265. +
  1266. +   /* Save level mapping */
  1267. +   ipl_table[vector] = level;
  1268. +
  1269. +   /*
  1270. +    * Unmask the target interrupt for all
  1271. +    * lower interrupt levels.
  1272. +    */
  1273. +   for (i = 0; i < level; i++)
  1274. +       mask_table[i][vector>>5] |= unmask;
  1275. +
  1276. +   update_mask();
  1277. +}
  1278. +
  1279. +/*
  1280. + * Mask interrupt in INTC for specified irq.
  1281. + * Interrupt must be disabled when this routine is called.
  1282. + */
  1283. +void
  1284. +interrupt_mask(int vector)
  1285. +{
  1286. +   int i, level;
  1287. +   uint32_t mask = (uint32_t)~(1 << (vector & 0x1f));
  1288. +
  1289. +   level = ipl_table[vector];
  1290. +
  1291. +   for (i = 0; i < level; i++)
  1292. +       mask_table[i][vector>>5] &= mask;
  1293. +
  1294. +   ipl_table[vector] = IPL_NONE;
  1295. +
  1296. +   update_mask();
  1297. +}
  1298. +
  1299. +/*
  1300. + * Setup interrupt mode.
  1301. + * Select whether an interrupt trigger is edge or level.
  1302. + */
  1303. +void
  1304. +interrupt_setup(int vector, int mode)
  1305. +{
  1306. +   /* nop */
  1307. +}
  1308. +
  1309. +/*
  1310. + * Common interrupt handler.
  1311. + */
  1312. +void
  1313. +interrupt_handler(void)
  1314. +{
  1315. +   uint32_t bits, threshold, priority;
  1316. +   int vector, old_ipl, new_ipl;
  1317. +
  1318. +   threshold = INTCPS_THRESHOLD;
  1319. +   priority = INTCPS_IRQ_PRIORITY & 0x3f;
  1320. +   INTCPS_THRESHOLD = priority;
  1321. +
  1322. +   bits = INTCPS_SIR_IRQ;      /* Get interrupt source */
  1323. +   if (bits >= NIRQS)      /* Ignore spurious interrupts */
  1324. +       goto out;
  1325. +   vector = bits & 0x7f;       /* Get device firing the interrupt */
  1326. +
  1327. +   /* Adjust interrupt level */
  1328. +   old_ipl = irq_level;
  1329. +   new_ipl = ipl_table[vector];
  1330. +   if (new_ipl > old_ipl)      /* Ignore spurious interrupt */
  1331. +       irq_level = new_ipl;
  1332. +   update_mask();
  1333. +
  1334. +   INTCPS_CONTROL = 0x01;      /* Allow new IRQ on INTC side */
  1335. +   mpu_intc_sync();            /* Data synchronization barrier */
  1336. +
  1337. +   /* Allow another interrupt that has higher priority */
  1338. +   splon();
  1339. +
  1340. +   /* Dispatch interrupt */
  1341. +   irq_handler(vector);
  1342. +
  1343. +   sploff();
  1344. +
  1345. +   /* Restore interrupt level */
  1346. +   irq_level = old_ipl;
  1347. +   update_mask();
  1348. +out:
  1349. +   INTCPS_THRESHOLD = threshold;
  1350. +   return;
  1351. +}
  1352. +
  1353. +/*
  1354. + * Initialize interrupt controllers.
  1355. + * All interrupts will be masked off.
  1356. + */
  1357. +void
  1358. +interrupt_init(void)
  1359. +{
  1360. +   int i,j;
  1361. +
  1362. +   irq_level = IPL_NONE;
  1363. +
  1364. +   for (i = 0; i < NIRQS; i++)
  1365. +       ipl_table[i] = IPL_NONE;
  1366. +
  1367. +   for (i = 0; i < NIPLS; i++)
  1368. +       for (j = 0; j < (NIRQS>>5); j++)
  1369. +           mask_table[i][j] = 0;
  1370. +
  1371. +   INTCPS_SYSCONFIG = 0x02;    /* Reset interrupt controller. This also masks all interrupts */
  1372. +
  1373. +   while (INTCPS_SYSSTATUS != 0x01) ;
  1374. +
  1375. +}
  1376. diff -aburN prex-0.9.0/bsp/hal/arm/beagle/locore_beagle.S prex-0.9.0-beagle/bsp/hal/arm/beagle/locore_beagle.S
  1377. --- prex-0.9.0/bsp/hal/arm/beagle/locore_beagle.S   1970-01-01 00:00:00 +0000
  1378. +++ prex-0.9.0-beagle/bsp/hal/arm/beagle/locore_beagle.S    2010-09-26 19:17:00 +0000
  1379. @@ -0,0 +1,77 @@
  1380. +/*-
  1381. + * Copyright (c) 2009-2010, Richard Pandion
  1382. + * All rights reserved.
  1383. + *
  1384. + * Redistribution and use in source and binary forms, with or without
  1385. + * modification, are permitted provided that the following conditions
  1386. + * are met:
  1387. + * 1. Redistributions of source code must retain the above copyright
  1388. + *    notice, this list of conditions and the following disclaimer.
  1389. + * 2. Redistributions in binary form must reproduce the above copyright
  1390. + *    notice, this list of conditions and the following disclaimer in the
  1391. + *    documentation and/or other materials provided with the distribution.
  1392. + * 3. Neither the name of the author nor the names of any co-contributors
  1393. + *    may be used to endorse or promote products derived from this software
  1394. + *    without specific prior written permission.
  1395. + *
  1396. + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  1397. + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  1398. + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  1399. + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  1400. + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  1401. + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  1402. + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  1403. + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  1404. + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  1405. + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  1406. + * SUCH DAMAGE.
  1407. + */
  1408. +
  1409. +/*
  1410. + * locore_machdep.S for TI OMAP3 SoC
  1411. + */
  1412. +
  1413. +#include <conf/config.h>
  1414. +#include <machine/asm.h>
  1415. +
  1416. +   .section ".text","ax"
  1417. +   .code 32
  1418. +
  1419. +/*
  1420. + * Data synchronization barrier for MPU INTC
  1421. + */
  1422. +ENTRY(mpu_intc_sync)
  1423. +   mov r0, #0
  1424. +   mcr p15, 0, r0, c7, c10, 4
  1425. +   mov pc, lr
  1426. +
  1427. +/*
  1428. + * Default exception vectors at 0x4020ffc8 (SRAM)
  1429. + * Use VBAR control register to change it
  1430. + */
  1431. +ENTRY(set_vbar)
  1432. +   mcr p15, 0, r0, c12, c0, 0
  1433. +   mov pc, lr
  1434. +
  1435. +/*
  1436. + * Reset system.
  1437. + */
  1438. +ENTRY(machine_reset)
  1439. +   /*
  1440. +    * Set MMU off...
  1441. +    */
  1442. +   mrc p15, 0, r0, c1, c0, 0
  1443. +   bic r0, r0, #0x01
  1444. +   mcr p15, 0, r0, c1, c0, 0
  1445. +  
  1446. +   /*
  1447. +    * ...then use control register to initiate reset command
  1448. +    */
  1449. +   ldr r0, =0x48307250
  1450. +   ldr r1, =0x02
  1451. +   str r1,[r0]
  1452. +   /* NOTREACHED */
  1453. +1:
  1454. +   b   1b
  1455. +
  1456. +   .end
  1457. diff -aburN prex-0.9.0/bsp/hal/arm/beagle/machdep.c prex-0.9.0-beagle/bsp/hal/arm/beagle/machdep.c
  1458. --- prex-0.9.0/bsp/hal/arm/beagle/machdep.c 1970-01-01 00:00:00 +0000
  1459. +++ prex-0.9.0-beagle/bsp/hal/arm/beagle/machdep.c  2010-09-26 19:17:06 +0000
  1460. @@ -0,0 +1,168 @@
  1461. +/*-
  1462. + * Copyright (c) 2009-2010, Richard Pandion
  1463. + * All rights reserved.
  1464. + *
  1465. + * Redistribution and use in source and binary forms, with or without
  1466. + * modification, are permitted provided that the following conditions
  1467. + * are met:
  1468. + * 1. Redistributions of source code must retain the above copyright
  1469. + *    notice, this list of conditions and the following disclaimer.
  1470. + * 2. Redistributions in binary form must reproduce the above copyright
  1471. + *    notice, this list of conditions and the following disclaimer in the
  1472. + *    documentation and/or other materials provided with the distribution.
  1473. + * 3. Neither the name of the author nor the names of any co-contributors
  1474. + *    may be used to endorse or promote products derived from this software
  1475. + *    without specific prior written permission.
  1476. + *
  1477. + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  1478. + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  1479. + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  1480. + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  1481. + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  1482. + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  1483. + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  1484. + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  1485. + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  1486. + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  1487. + * SUCH DAMAGE.
  1488. + */
  1489. +
  1490. +/*
  1491. + * machdep.c - machine-dependent routines for Beagle Board
  1492. + */
  1493. +
  1494. +#include <machine/syspage.h>
  1495. +#include <sys/power.h>
  1496. +#include <sys/bootinfo.h>
  1497. +#include <kernel.h>
  1498. +#include <page.h>
  1499. +#include <mmu.h>
  1500. +#include <cpu.h>
  1501. +#include <cpufunc.h>
  1502. +#include <locore.h>
  1503. +
  1504. +#include "platform.h"
  1505. +
  1506. +#ifdef CONFIG_MMU
  1507. +/*
  1508. + * Virtual and physical address mapping
  1509. + *
  1510. + *      { virtual, physical, size, type }
  1511. + */
  1512. +struct mmumap mmumap_table[] =
  1513. +{
  1514. +   /*
  1515. +    * Q1 :
  1516. +    *  Boot ROM            (112 KB)
  1517. +    *  SRAM                ( 64 KB)
  1518. +    *  L4 Interconnects    ( 17 MB)
  1519. +    *  SGX                 ( 64 KB)
  1520. +    *  L4 Emulation        (  8 MB)
  1521. +    *  IVA2.2 SS           ( 48 MB)
  1522. +    *  L3 control regs     ( 16 MB)
  1523. +    *  SMS, SRDC, GPMC
  1524. +    *    control regs      ( 48 MB)
  1525. +    */
  1526. +   { 0xa0000000, 0x40000000, 0x0001C000, VMT_ROM },
  1527. +   { 0xa0200000, 0x40200000, 0x00010000, VMT_RAM },
  1528. +   { 0xa8000000, 0x48000000, 0x01100000, VMT_IO  },
  1529. +   { 0xb0000000, 0x50000000, 0x00010000, VMT_IO  },
  1530. +   { 0xb4000000, 0x54000000, 0x00800000, VMT_IO  },
  1531. +   { 0xbC000000, 0x5C000000, 0x03000000, VMT_IO  },
  1532. +   { 0xc8000000, 0x68000000, 0x01000000, VMT_IO  },
  1533. +   { 0xcC000000, 0x6C000000, 0x03000000, VMT_IO  },
  1534. +
  1535. +   /*
  1536. +    * Q2: SDRAM (512 MB)
  1537. +    * Although Q2 is 1 GB in size we only map 512 MB
  1538. +    * as this is the max ram size on the Beagle Board
  1539. +    */
  1540. +   { 0x80000000, 0x80000000, 0x20000000, VMT_RAM },
  1541. +
  1542. +   { 0,0,0,0 }
  1543. +};
  1544. +#endif
  1545. +
  1546. +/*
  1547. + * Idle
  1548. + */
  1549. +void
  1550. +machine_idle(void)
  1551. +{
  1552. +
  1553. +   cpu_idle();
  1554. +}
  1555. +
  1556. +/*
  1557. + * Set system power
  1558. + */
  1559. +void
  1560. +machine_powerdown(int state)
  1561. +{
  1562. +
  1563. +   splhigh();
  1564. +
  1565. +   DPRINTF(("Power down machine\n"));
  1566. +
  1567. +   switch (state) {
  1568. +   case PWR_OFF:
  1569. +       for (;;)
  1570. +           cpu_idle();
  1571. +       /* NOTREACHED */
  1572. +       break;
  1573. +   case PWR_REBOOT:
  1574. +       machine_reset();
  1575. +       /* NOTREACHED */
  1576. +       break;
  1577. +   }
  1578. +}
  1579. +
  1580. +/*
  1581. + * Return pointer to the boot information.
  1582. + */
  1583. +void
  1584. +machine_bootinfo(struct bootinfo **bip)
  1585. +{
  1586. +
  1587. +   *bip = (struct bootinfo *)BOOTINFO;
  1588. +}
  1589. +
  1590. +void
  1591. +machine_abort(void)
  1592. +{
  1593. +
  1594. +   for (;;)
  1595. +       cpu_idle();
  1596. +}
  1597. +
  1598. +/*
  1599. + * Machine-dependent startup code
  1600. + */
  1601. +void
  1602. +machine_startup(void)
  1603. +{
  1604. +
  1605. +   /*
  1606. +    * Initialize CPU and basic hardware.
  1607. +    */
  1608. +   cpu_init();
  1609. +   cache_init();
  1610. +
  1611. +   /*
  1612. +    * Reserve system pages.
  1613. +    */
  1614. +   page_reserve(kvtop(SYSPAGE), SYSPAGESZ);
  1615. +
  1616. +   /*
  1617. +    * Setup vector page.
  1618. +    */
  1619. +   vector_copy((vaddr_t)ptokv(CONFIG_ARM_VECTORS));
  1620. +   set_vbar((vaddr_t)ptokv(CONFIG_ARM_VECTORS));
  1621. +
  1622. +#ifdef CONFIG_MMU
  1623. +   /*
  1624. +    * Initialize MMU
  1625. +    */
  1626. +   mmu_init(mmumap_table);
  1627. +#endif
  1628. +}
  1629. diff -aburN prex-0.9.0/bsp/hal/arm/beagle/platform.h prex-0.9.0-beagle/bsp/hal/arm/beagle/platform.h
  1630. --- prex-0.9.0/bsp/hal/arm/beagle/platform.h    1970-01-01 00:00:00 +0000
  1631. +++ prex-0.9.0-beagle/bsp/hal/arm/beagle/platform.h 2010-09-26 19:17:14 +0000
  1632. @@ -0,0 +1,65 @@
  1633. +/*
  1634. + * Copyright (c) 2009-2010, Richard Pandion
  1635. + * All rights reserved.
  1636. + *
  1637. + * Redistribution and use in source and binary forms, with or without
  1638. + * modification, are permitted provided that the following conditions
  1639. + * are met:
  1640. + * 1. Redistributions of source code must retain the above copyright
  1641. + *    notice, this list of conditions and the following disclaimer.
  1642. + * 2. Redistributions in binary form must reproduce the above copyright
  1643. + *    notice, this list of conditions and the following disclaimer in the
  1644. + *    documentation and/or other materials provided with the distribution.
  1645. + * 3. Neither the name of the author nor the names of any co-contributors
  1646. + *    may be used to endorse or promote products derived from this software
  1647. + *    without specific prior written permission.
  1648. + *
  1649. + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  1650. + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  1651. + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  1652. + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  1653. + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  1654. + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  1655. + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  1656. + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  1657. + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  1658. + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  1659. + * SUCH DAMAGE.
  1660. + */
  1661. +
  1662. +#ifndef _BEAGLE_PLATFORM_H
  1663. +#define _BEAGLE_PLATFORM_H
  1664. +
  1665. +/* number of interrupt vectors */
  1666. +#define NIRQS      96
  1667. +
  1668. +#ifdef CONFIG_MMU
  1669. +/* base address for L4 Peripherals registers */
  1670. +#define L4_Per     0xa9000000
  1671. +/* base address for L4 Core registers */
  1672. +#define L4_Core        0xa8000000
  1673. +#else
  1674. +/* base address for L4 Peripherals registers */
  1675. +#define L4_Per     0x49000000
  1676. +/* base address for L4 Core registers */
  1677. +#define L4_Core        0x48000000
  1678. +#endif
  1679. +
  1680. +#define L4_PRCM_CM (L4_Core + 0x4000)
  1681. +#define L4_MPU_INTC    (L4_Core + 0x200000)
  1682. +
  1683. +#define L4_UART3   (L4_Per  + 0x20000)
  1684. +#define L4_GPTIMER2    (L4_Per  + 0x32000)
  1685. +
  1686. +#define UART_BASE  L4_UART3
  1687. +#define TIMER_BASE L4_GPTIMER2
  1688. +#define MPU_INTC_BASE  L4_MPU_INTC
  1689. +#define    PER_CM_BASE     (L4_PRCM_CM + 0x1000)
  1690. +
  1691. +__BEGIN_DECLS
  1692. +void    mpu_intc_sync(void);
  1693. +void    set_vbar(vaddr_t);
  1694. +void    machine_reset(void);
  1695. +__END_DECLS
  1696. +
  1697. +#endif /* !_BEAGLE_PLATFORM_H */
  1698. diff -aburN prex-0.9.0/bsp/hal/arm/include/cpu.h prex-0.9.0-beagle/bsp/hal/arm/include/cpu.h
  1699. --- prex-0.9.0/bsp/hal/arm/include/cpu.h    2009-07-09 10:42:02 +0000
  1700. +++ prex-0.9.0-beagle/bsp/hal/arm/include/cpu.h 2010-09-26 19:19:46 +0000
  1701. @@ -1,5 +1,6 @@
  1702.  /*-
  1703.   * Copyright (c) 2005-2008, Kohsuke Ohtani
  1704. + * Copyright (c) 2010, Richard Pandion
  1705.   * All rights reserved.
  1706.   *
  1707.   * Redistribution and use in source and binary forms, with or without
  1708. @@ -55,23 +56,31 @@
  1709.  #endif
  1710.  
  1711.  /*
  1712. - * Contorl register CP15 register 1
  1713. + * Control register CP15 register 1
  1714.   */
  1715. -#define CTL_MMU        0x000000001 /* M: MMU/Protection unit enable */
  1716. -#define CTL_AFLT   0x000000002 /* A: Alignment fault enable */
  1717. -#define CTL_CACHE  0x000000004 /* C: Cache enable */
  1718. -#define CTL_WBUF   0x000000008 /* W: Write buffer enable */
  1719. -#define CTL_32BP   0x000000010 /* P: 32-bit exception handlers */
  1720. -#define CTL_32BD   0x000000020 /* D: 32-bit addressing */
  1721. -#define CTL_LABT   0x000000040 /* L: Late abort enable */
  1722. -#define CTL_BIGEND 0x000000080 /* B: Big-endian mode */
  1723. -#define CTL_SYSP   0x000000100 /* S: System protection bit */
  1724. -#define CTL_ROMP   0x000000200 /* R: ROM protection bit */
  1725. -#define CTL_BPRD   0x000000800 /* Z: Branch prediction enable */
  1726. -#define CTL_ICACHE 0x000001000 /* I: Instruction cache enable */
  1727. -#define CTL_HIVEC  0x000002000 /* V: Vector relocation */
  1728. -
  1729. -#define CTL_DEFAULT    (CTL_32BP | CTL_32BD | CTL_LABT)
  1730. +#define CTL_MMU        0x00000001  /* M: MMU/Protection unit enable */
  1731. +#define CTL_AFLT   0x00000002  /* A: Alignment fault enable */
  1732. +#define CTL_CACHE  0x00000004  /* C: Cache enable */
  1733. +#define CTL_WBUF   0x00000008  /* W: Write buffer enable */
  1734. +#define CTL_32BP   0x00000010  /* P: 32-bit exception handlers */
  1735. +#define CTL_32BD   0x00000020  /* D: 32-bit addressing */
  1736. +#define CTL_LABT   0x00000040  /* L: Late abort enable */
  1737. +#define CTL_BIGEND 0x00000080  /* B: Big-endian mode */
  1738. +#define CTL_SYSP   0x00000100  /* S: System protection bit */
  1739. +#define CTL_ROMP   0x00000200  /* R: ROM protection bit */
  1740. +#define CTL_BPRD   0x00000800  /* Z: Branch prediction enable */
  1741. +#define CTL_ICACHE 0x00001000  /* I: Instruction cache enable */
  1742. +#define CTL_HIVEC  0x00002000  /* V: Vector relocation */
  1743. +
  1744. +#ifdef __beagle__
  1745. +/* Useful ARMv7 specific flags */
  1746. +#define CTL_AFE        0x20000000  /* AFE: Access flag enable */
  1747. +#define CTL_TRE        0x10000000  /* TRE: TEX remap enable */
  1748. +#define    AUXCTL_L2EN 0x00000002  /* L2EN: L2 cache enable */
  1749. +#define    AUXCTL_ASA  0x00000010  /* ASA: Speculative access enable */
  1750. +#define    AUXCTL_IBE  0x00000040  /* IBE: */
  1751. +#define    AUXCTL_BTB  0x00000080  /* BTB: */
  1752. +#endif
  1753.  
  1754.  #ifndef __ASSEMBLY__
  1755.  
  1756. diff -aburN prex-0.9.0/bsp/hal/arm/include/mmu.h prex-0.9.0-beagle/bsp/hal/arm/include/mmu.h
  1757. --- prex-0.9.0/bsp/hal/arm/include/mmu.h    2009-10-01 12:28:54 +0000
  1758. +++ prex-0.9.0-beagle/bsp/hal/arm/include/mmu.h 2010-09-26 19:20:12 +0000
  1759. @@ -1,5 +1,6 @@
  1760.  /*-
  1761.   * Copyright (c) 2005-2008, Kohsuke Ohtani
  1762. + * Copyright (c) 2010, Richard Pandion
  1763.   * All rights reserved.
  1764.   *
  1765.   * Redistribution and use in source and binary forms, with or without
  1766. @@ -36,25 +37,36 @@
  1767.  typedef uint32_t   *pte_t;     /* page table entry */
  1768.  
  1769.  #define L1TBL_SIZE 0x4000
  1770. -#define L2TBL_SIZE 0x1000
  1771. +#define L2TBL_SIZE 0x400
  1772.  
  1773.  /*
  1774.   * Page directory entry (L1)
  1775.   */
  1776. -#define PDE_PRESENT    0x00000003
  1777. -#define PDE_ADDRESS    0xfffff000
  1778. +#define PDE_PRESENT    0x00000001
  1779. +#define PDE_ADDRESS    0xfffffc00
  1780.  
  1781.  /*
  1782.   * Page table entry (L2)
  1783.   */
  1784. +#ifdef __beagle__
  1785.  #define PTE_PRESENT    0x00000002
  1786.  #define PTE_WBUF   0x00000004
  1787.  #define PTE_CACHE  0x00000008
  1788.  #define PTE_SYSTEM 0x00000010
  1789.  #define PTE_USER_RO    0x00000020
  1790.  #define PTE_USER_RW    0x00000030
  1791. -#define PTE_ATTR_MASK  0x00000030
  1792. -#define PTE_ADDRESS    0xfffffc00
  1793. +#define PTE_ATTR_MASK  0x00000ff0
  1794. +#define PTE_ADDRESS    0xfffff000
  1795. +#else
  1796. +#define PTE_PRESENT    0x00000002
  1797. +#define PTE_WBUF   0x00000004
  1798. +#define PTE_CACHE  0x00000008
  1799. +#define PTE_SYSTEM 0x00000550
  1800. +#define PTE_USER_RO    0x00000aa0
  1801. +#define PTE_USER_RW    0x00000ff0
  1802. +#define PTE_ATTR_MASK  0x00000ff0
  1803. +#define PTE_ADDRESS    0xfffff000
  1804. +#endif
  1805.  
  1806.  /*
  1807.   *  Virtual and physical address translation
  1808. diff -aburN prex-0.9.0/conf/arm/beagle prex-0.9.0-beagle/conf/arm/beagle
  1809. --- prex-0.9.0/conf/arm/beagle  1970-01-01 00:00:00 +0000
  1810. +++ prex-0.9.0-beagle/conf/arm/beagle   2010-07-31 21:17:34 +0000
  1811. @@ -0,0 +1,131 @@
  1812. +#
  1813. +# Prex system configuration file
  1814. +#
  1815. +
  1816. +#
  1817. +# Make options
  1818. +#
  1819. +#makeoptions   CFLAGS+= -mfpu=neon -mfloat-abi=softfp -mcpu=cortex-a8 -fno-math-errno -fno-tree-vectorize
  1820. +makeoptions    CFLAGS+= -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp
  1821. +makeoptions    ASLAGS+= -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp
  1822. +#
  1823. +# Memory address
  1824. +#
  1825. +memory     RAM_BASE        0x80000000  # Start of ram
  1826. +memory     LOADER_TEXT     0x80300000  # Start of boot loader
  1827. +memory     KERNEL_TEXT     0x80080000  # Start of kernel
  1828. +memory     BOOTIMG_BASE    0x80302000  # Location of boot image
  1829. +memory     SYSPAGE_BASE    0x80000000  # Location of system page
  1830. +
  1831. +#
  1832. +# Tunable paramters
  1833. +#
  1834. +options    HZ=1000         # Ticks/second of the clock
  1835. +options    TIME_SLICE=50   # Context switch ratio (msec)
  1836. +options    OPEN_MAX=16     # Max open files per process
  1837. +options    BUF_CACHE=32    # Blocks for buffer cache
  1838. +options    FS_THREADS=4    # Number of file system threads
  1839. +
  1840. +#
  1841. +# Platform settings
  1842. +#
  1843. +#options       ARMV7-A     # Processor core
  1844. +options    MMU         # Memory management unit
  1845. +options    CACHE       # Cache memory
  1846. +#options   FPU         # Floating point unit
  1847. +#options   ROMBOOT     # Boot from ROM
  1848. +options    BOOTDISK    # Disk for /boot directory
  1849. +
  1850. +#
  1851. +# General setup
  1852. +#
  1853. +options    POSIX       # POSIX support
  1854. +options    CMDBOX      # Core utilities
  1855. +#options   TINY        # Optimize for size
  1856. +
  1857. +#
  1858. +# Kernel hacking
  1859. +#
  1860. +#options   KD      # Kernel debugger
  1861. +#options   AUDIT       # Security auditing
  1862. +
  1863. +#
  1864. +# Diagnostic options
  1865. +#
  1866. +options    DIAG_SERIAL # Diagnostic via serial port
  1867. +
  1868. +#
  1869. +# File systems
  1870. +#
  1871. +options    FIFOFS      # FIFO & Pipe
  1872. +options    DEVFS       # Device file system
  1873. +options    RAMFS       # RAM file system
  1874. +options    ARFS        # Archive file system
  1875. +#options   FATFS       # FAT file system
  1876. +
  1877. +#
  1878. +# Power management
  1879. +#
  1880. +#options   PM              # Power management
  1881. +#options   PM_POWERSAVE    # Power policy: Battery optimized
  1882. +#options   PM_PERFORMANCE  # Power policy: Parformance optimized
  1883. +
  1884. +#
  1885. +# Device drivers (initialization order)
  1886. +#
  1887. +device     pm          # Power management
  1888. +device     cons        # System console
  1889. +device     serial      # Logical serial
  1890. +device     omap3_uart  # OMAP3_UART serial port (P:serial)
  1891. +device     null        # NULL device
  1892. +device     zero        # Zero device
  1893. +device     ramdisk     # RAM disk
  1894. +
  1895. +#
  1896. +# Hardware configuations
  1897. +#
  1898. +#options       ARM_VECTORS=0x4020FFC8
  1899. +options        ARM_VECTORS=0x80000000
  1900. +options        OMAP3_UART_BASE=0xa9020000
  1901. +options        OMAP3_UART_IRQ=74
  1902. +
  1903. +
  1904. +#
  1905. +# Command box
  1906. +#
  1907. +command    cat
  1908. +command    clear
  1909. +command    cp
  1910. +command    date
  1911. +command    dmesg
  1912. +command    echo
  1913. +command    free
  1914. +command    head
  1915. +command    hostname
  1916. +command    kill
  1917. +command    ls
  1918. +command    mkdir
  1919. +command    more
  1920. +command    mv
  1921. +command    nice
  1922. +command    printenv
  1923. +command    ps
  1924. +command    pwd
  1925. +command    rm
  1926. +command    rmdir
  1927. +command    sh
  1928. +command    sleep
  1929. +command    sync
  1930. +#command   test
  1931. +command    touch
  1932. +command    uname
  1933. +
  1934. +#
  1935. +# Adminisrative tools
  1936. +#
  1937. +command    diskutil
  1938. +command    install
  1939. +command    pmctrl
  1940. +command    ktrace
  1941. +command    lock
  1942. +command    debug
  1943. diff -aburN prex-0.9.0/conf/arm/beagle-nommu prex-0.9.0-beagle/conf/arm/beagle-nommu
  1944. --- prex-0.9.0/conf/arm/beagle-nommu    1970-01-01 00:00:00 +0000
  1945. +++ prex-0.9.0-beagle/conf/arm/beagle-nommu 2010-07-20 16:07:22 +0000
  1946. @@ -0,0 +1,131 @@
  1947. +#
  1948. +# Prex system configuration file
  1949. +#
  1950. +
  1951. +#
  1952. +# Make options
  1953. +#
  1954. +#makeoptions   CFLAGS+= -mfpu=neon -mfloat-abi=softfp -mcpu=cortex-a8 -fno-math-errno -fno-tree-vectorize
  1955. +makeoptions    CFLAGS+= -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp
  1956. +makeoptions    ASLAGS+= -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp
  1957. +#
  1958. +# Memory address
  1959. +#
  1960. +memory     RAM_BASE        0x80000000  # Start of ram
  1961. +memory     LOADER_TEXT     0x80300000  # Start of boot loader
  1962. +memory     KERNEL_TEXT     0x80080000  # Start of kernel
  1963. +memory     BOOTIMG_BASE    0x80302000  # Location of boot image
  1964. +memory     SYSPAGE_BASE    0x80000000  # Location of system page
  1965. +
  1966. +#
  1967. +# Tunable paramters
  1968. +#
  1969. +options    HZ=1000         # Ticks/second of the clock
  1970. +options    TIME_SLICE=50   # Context switch ratio (msec)
  1971. +options    OPEN_MAX=16     # Max open files per process
  1972. +options    BUF_CACHE=32    # Blocks for buffer cache
  1973. +options    FS_THREADS=4    # Number of file system threads
  1974. +
  1975. +#
  1976. +# Platform settings
  1977. +#
  1978. +#options       ARMV7-A     # Processor core
  1979. +#options   MMU         # Memory management unit
  1980. +options    CACHE       # Cache memory
  1981. +#options   FPU         # Floating point unit
  1982. +#options   ROMBOOT     # Boot from ROM
  1983. +options    BOOTDISK    # Disk for /boot directory
  1984. +
  1985. +#
  1986. +# General setup
  1987. +#
  1988. +options    POSIX       # POSIX support
  1989. +options    CMDBOX      # Core utilities
  1990. +#options   TINY        # Optimize for size
  1991. +
  1992. +#
  1993. +# Kernel hacking
  1994. +#
  1995. +#options   KD      # Kernel debugger
  1996. +#options   AUDIT       # Security auditing
  1997. +
  1998. +#
  1999. +# Diagnostic options
  2000. +#
  2001. +options    DIAG_SERIAL # Diagnostic via serial port
  2002. +
  2003. +#
  2004. +# File systems
  2005. +#
  2006. +options    FIFOFS      # FIFO & Pipe
  2007. +options    DEVFS       # Device file system
  2008. +options    RAMFS       # RAM file system
  2009. +options    ARFS        # Archive file system
  2010. +#options   FATFS       # FAT file system
  2011. +
  2012. +#
  2013. +# Power management
  2014. +#
  2015. +#options   PM              # Power management
  2016. +#options   PM_POWERSAVE    # Power policy: Battery optimized
  2017. +#options   PM_PERFORMANCE  # Power policy: Parformance optimized
  2018. +
  2019. +#
  2020. +# Device drivers (initialization order)
  2021. +#
  2022. +device     pm          # Power management
  2023. +device     cons        # System console
  2024. +device     serial      # Logical serial
  2025. +device     omap3_uart  # OMAP3_UART serial port (P:serial)
  2026. +device     null        # NULL device
  2027. +device     zero        # Zero device
  2028. +device     ramdisk     # RAM disk
  2029. +
  2030. +#
  2031. +# Hardware configuations
  2032. +#
  2033. +#options       ARM_VECTORS=0x4020FFC8
  2034. +options        ARM_VECTORS=0x80000000
  2035. +options        OMAP3_UART_BASE=0x49020000
  2036. +options        OMAP3_UART_IRQ=74
  2037. +
  2038. +
  2039. +#
  2040. +# Command box
  2041. +#
  2042. +command    cat
  2043. +command    clear
  2044. +command    cp
  2045. +command    date
  2046. +command    dmesg
  2047. +command    echo
  2048. +command    free
  2049. +command    head
  2050. +command    hostname
  2051. +command    kill
  2052. +command    ls
  2053. +command    mkdir
  2054. +command    more
  2055. +command    mv
  2056. +command    nice
  2057. +command    printenv
  2058. +command    ps
  2059. +command    pwd
  2060. +command    rm
  2061. +command    rmdir
  2062. +command    sh
  2063. +command    sleep
  2064. +command    sync
  2065. +#command   test
  2066. +command    touch
  2067. +command    uname
  2068. +
  2069. +#
  2070. +# Adminisrative tools
  2071. +#
  2072. +command    diskutil
  2073. +command    install
  2074. +command    pmctrl
  2075. +command    ktrace
  2076. +command    lock
  2077. +command    debug
  2078. diff -aburN prex-0.9.0/conf/arm/integrator prex-0.9.0-beagle/conf/arm/integrator
  2079. --- prex-0.9.0/conf/arm/integrator  2009-09-24 09:51:40 +0000
  2080. +++ prex-0.9.0-beagle/conf/arm/integrator   2010-09-27 16:33:36 +0000
  2081. @@ -11,6 +11,7 @@
  2082.  #
  2083.  # Memory address
  2084.  #
  2085. +memory     RAM_BASE    0x00000000  # Start of RAM
  2086.  memory     LOADER_TEXT 0x00010000  # Start of boot loader
  2087.  memory     KERNEL_TEXT 0x80080000  # Start of kernel
  2088.  memory     BOOTIMG_BASE    0x80012000  # Location of boot image
  2089. diff -aburN prex-0.9.0/conf/arm/integrator-nommu prex-0.9.0-beagle/conf/arm/integrator-nommu
  2090. --- prex-0.9.0/conf/arm/integrator-nommu    2009-09-24 09:51:38 +0000
  2091. +++ prex-0.9.0-beagle/conf/arm/integrator-nommu 2010-09-24 16:36:04 +0000
  2092. @@ -11,6 +11,7 @@
  2093.  #
  2094.  # Memory address
  2095.  #
  2096. +memory     RAM_BASE    0x00000000  # Start of RAM
  2097.  memory     LOADER_TEXT 0x00010000  # Start of boot loader
  2098.  memory     KERNEL_TEXT 0x00080000  # Start of kernel
  2099.  memory     BOOTIMG_BASE    0x00012000  # Location of boot image
  2100. diff -aburN prex-0.9.0/conf/etc/fstab prex-0.9.0-beagle/conf/etc/fstab
  2101. --- prex-0.9.0/conf/etc/fstab   2009-10-01 12:31:56 +0000
  2102. +++ prex-0.9.0-beagle/conf/etc/fstab    2010-01-21 15:31:00 +0000
  2103. @@ -6,7 +6,7 @@
  2104.  /dev/ram0  /boot       arfs
  2105.  none       /dev        devfs
  2106.  none       /mnt/fifo   fifofs
  2107. -/dev/fd0   /mnt/floppy fatfs
  2108. +#/dev/fd0  /mnt/floppy fatfs
  2109.  
  2110.  #/dev/mtd0 /bin        ffs
  2111.  #/dev/mtd1 /etc        ffs
  2112. diff -aburN prex-0.9.0/configure prex-0.9.0-beagle/configure
  2113. --- prex-0.9.0/configure    2009-10-01 12:18:40 +0000
  2114. +++ prex-0.9.0-beagle/configure 2010-07-14 15:52:44 +0000
  2115. @@ -185,17 +185,6 @@
  2116.         objdump="gobjdump"
  2117.         ;;
  2118.     CYGWIN*|MINGW*)
  2119. -       case "$arch" in
  2120. -       x86)
  2121. -           prefix="i386-elf-"
  2122. -           ;;
  2123. -       ppc)
  2124. -           prefix="powerpc-elf-"
  2125. -           ;;
  2126. -       *)
  2127. -           prefix="$arch-elf-"
  2128. -           ;;
  2129. -       esac
  2130.         ;;
  2131.     esac
  2132.  
  2133. diff -aburN prex-0.9.0/include/arm/elf.h prex-0.9.0-beagle/include/arm/elf.h
  2134. --- prex-0.9.0/include/arm/elf.h    2009-06-28 23:46:40 +0000
  2135. +++ prex-0.9.0-beagle/include/arm/elf.h 2010-08-05 10:56:38 +0000
  2136. @@ -39,5 +39,6 @@
  2137.  #define    R_ARM_PLT32 27
  2138.  #define    R_ARM_CALL  28
  2139.  #define R_ARM_JUMP24   29
  2140. +#define R_ARM_V4BX  40
  2141.  
  2142.  #endif /* !_ARM_ELF_H */
  2143. diff -aburN prex-0.9.0/include/arm/memory.h prex-0.9.0-beagle/include/arm/memory.h
  2144. --- prex-0.9.0/include/arm/memory.h 2009-10-01 12:03:56 +0000
  2145. +++ prex-0.9.0-beagle/include/arm/memory.h  2010-07-24 08:52:52 +0000
  2146. @@ -33,11 +33,13 @@
  2147.  #include <conf/config.h>
  2148.  
  2149.  #ifdef CONFIG_MMU
  2150. -#define KERNBASE   0x80000000  /* offset of kernel address space */
  2151. +#define KERNBASE   CONFIG_SYSPAGE_BASE /* base address of kernel address space */
  2152. +#define KERNOFFSET (KERNBASE - CONFIG_RAM_BASE)    /* offset of kernel address space from RAM base */
  2153.  #define PAGE_SIZE  4096        /* bytes per page */
  2154. -#define USERLIMIT  0x80000000  /* upper limit on user address space */
  2155. +#define USERLIMIT  CONFIG_SYSPAGE_BASE /* upper limit on user address space */
  2156.  #else
  2157. -#define KERNBASE   0       /* offset of kernel address space */
  2158. +#define KERNBASE   0       /* base address of kernel address space */
  2159. +#define KERNOFFSET 0       /* offset of kernel address space from RAM base */
  2160.  #define PAGE_SIZE  1024        /* bytes per page */
  2161.  #define USERLIMIT  0xffffffff  /* upper limit on user address space */
  2162.  #endif
  2163. diff -aburN prex-0.9.0/include/arm/syspage.h prex-0.9.0-beagle/include/arm/syspage.h
  2164. --- prex-0.9.0/include/arm/syspage.h    2009-05-14 12:23:00 +0000
  2165. +++ prex-0.9.0-beagle/include/arm/syspage.h 2010-07-23 19:24:12 +0000
  2166. @@ -81,9 +81,10 @@
  2167.  #define BOOT_PTE0  (SYSPAGE + 0x8000)
  2168.  #define BOOT_PTE1  (SYSPAGE + 0x9000)
  2169.  
  2170. -#define BOOT_PGD_PHYS  0x4000
  2171. -#define BOOT_PTE0_PHYS 0x8000
  2172. -#define BOOT_PTE1_PHYS 0x9000
  2173. +#define RAMBASE        CONFIG_RAM_BASE
  2174. +#define BOOT_PGD_PHYS  (RAMBASE + 0x4000)
  2175. +#define BOOT_PTE0_PHYS (RAMBASE + 0x8000)
  2176. +#define BOOT_PTE1_PHYS (RAMBASE + 0x9000)
  2177.  
  2178.  #define INTSTKSZ   0x1000
  2179.  #define SYSSTKSZ   0x1000
  2180. diff -aburN prex-0.9.0/include/sys/param.h prex-0.9.0-beagle/include/sys/param.h
  2181. --- prex-0.9.0/include/sys/param.h  2009-10-01 12:17:30 +0000
  2182. +++ prex-0.9.0-beagle/include/sys/param.h   2010-09-24 16:37:20 +0000
  2183. @@ -68,7 +68,11 @@
  2184.  #define MAXEVTNAME 12      /* max event name */
  2185.  
  2186.  #define HZ     CONFIG_HZ   /* ticks per second */
  2187. +#ifdef __beagle__
  2188. +#define MAXIRQS        96      /* max number of irq line */
  2189. +#else
  2190.  #define MAXIRQS        32      /* max number of irq line */
  2191. +#endif
  2192.  #define    PASSWORD_LEN    4       /* fixed length, not counting NULL */
  2193.  
  2194.  /*
  2195. @@ -124,9 +128,9 @@
  2196.  #define user_area(a)   1
  2197.  #endif
  2198.  
  2199. -/* Address translation between physical address and kernel viritul address */
  2200. -#define ptokv(pa)  (void *)((paddr_t)(pa) + KERNBASE)
  2201. -#define kvtop(va)  ((paddr_t)(va) - KERNBASE)
  2202. +/* Address translation between physical address and kernel virtual address */
  2203. +#define ptokv(pa)  (void *)((paddr_t)(pa) + KERNOFFSET)
  2204. +#define kvtop(va)  ((paddr_t)(va) - KERNOFFSET)
  2205.  
  2206.  /*
  2207.   * Round p (pointer or byte index) up to a correctly-aligned value for all
  2208. diff -aburN prex-0.9.0/sys/sync/sem.c prex-0.9.0-beagle/sys/sync/sem.c
  2209. --- prex-0.9.0/sys/sync/sem.c   2009-10-01 12:34:20 +0000
  2210. +++ prex-0.9.0-beagle/sys/sync/sem.c    2010-07-14 17:13:44 +0000
  2211. @@ -77,7 +77,7 @@
  2212.      * whether the semaphore is already allocated.
  2213.      */
  2214.     sched_lock();
  2215. -   if (sem_valid(s)) {
  2216. +   if (s && sem_valid(s)) {
  2217.         /*
  2218.          * Semaphore already exists.
  2219.          */
  2220. diff -aburN prex-0.9.0/usr/arch/arm/elf_reloc.c prex-0.9.0-beagle/usr/arch/arm/elf_reloc.c
  2221. --- prex-0.9.0/usr/arch/arm/elf_reloc.c 2009-07-17 10:40:32 +0000
  2222. +++ prex-0.9.0-beagle/usr/arch/arm/elf_reloc.c  2010-08-05 10:59:04 +0000
  2223. @@ -56,6 +56,9 @@
  2224.         *where = (*where & 0xff000000) | (tmp & 0x00ffffff);
  2225.         /* printf("R_ARM_PC24: %x -> %x\n", where, *where); */
  2226.         break;
  2227. +   case R_ARM_V4BX:
  2228. +       /* nothing to do: bx instruction is supported */
  2229. +       break;
  2230.     default:
  2231.  #ifdef DEBUG
  2232.         syslog(LOG_ERR, "relocation fail type=%d\n", ELF32_R_TYPE(rel->r_info));
  2233. diff -aburN prex-0.9.0/usr/sbin/init/init.c prex-0.9.0-beagle/usr/sbin/init/init.c
  2234. --- prex-0.9.0/usr/sbin/init/init.c 2009-10-01 12:19:28 +0000
  2235. +++ prex-0.9.0-beagle/usr/sbin/init/init.c  2010-09-28 12:57:12 +0000
  2236. @@ -87,7 +87,7 @@
  2237.         dup(0);         /* stderr */
  2238.  
  2239.         sys_log("init: running boot script\n");
  2240. -       execl(cmdbox, sh, runcom);
  2241. +       execl(cmdbox, sh, runcom, NULL);
  2242.         sys_panic("init: no shell");
  2243.     }
  2244.  
  2245. diff -aburN prex-0.9.0/usr/server/exec/exec_elf.c prex-0.9.0-beagle/usr/server/exec/exec_elf.c
  2246. --- prex-0.9.0/usr/server/exec/exec_elf.c   2009-07-17 10:55:58 +0000
  2247. +++ prex-0.9.0-beagle/usr/server/exec/exec_elf.c    2010-08-05 11:01:38 +0000
  2248. @@ -116,7 +116,10 @@
  2249.  
  2250.     for (i = 0; i < nr_reloc; i++) {
  2251.         sym = &sym_table[ELF32_R_SYM(rela->r_info)];
  2252. -       if (sym->st_shndx != STN_UNDEF) {
  2253. +       if (sym->st_info == 0) {
  2254. +           /* Empty symbol used for R_ARM_V4BX, etc */
  2255. +           sym_val = sym->st_value;
  2256. +       } else if (sym->st_shndx != STN_UNDEF) {
  2257.             sym_val = (Elf32_Addr)sect_addr[sym->st_shndx]
  2258.                 + sym->st_value;
  2259.             if (relocate_rela(rela, sym_val, target_sect) != 0)
  2260. @@ -139,7 +142,10 @@
  2261.  
  2262.     for (i = 0; i < nr_reloc; i++) {
  2263.         sym = &sym_table[ELF32_R_SYM(rel->r_info)];
  2264. -       if (sym->st_shndx != STN_UNDEF) {
  2265. +       if (sym->st_info == 0) {
  2266. +           /* Empty symbol used for R_ARM_V4BX, etc */
  2267. +           sym_val = sym->st_value;
  2268. +       } else if (sym->st_shndx != STN_UNDEF) {
  2269.             sym_val = (Elf32_Addr)sect_addr[sym->st_shndx]
  2270.                 + sym->st_value;
  2271.             if (relocate_rel(rel, sym_val, target_sect) != 0)
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