From e6b7ccf8a9ee96157ac93df60545ad583ad01041 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Tue, 26 Mar 2013 00:19:32 -0300
Subject: [PATCH] mx6: Fix the reading of CPU version

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 arch/arm/cpu/armv7/mx6/soc.c              |   28 ++++++++++++----------------
 arch/arm/imx-common/cpu.c                 |   10 ++++------
 arch/arm/include/asm/arch-mx5/sys_proto.h |    6 +++---
 arch/arm/include/asm/arch-mx6/sys_proto.h |    5 ++---
 4 files changed, 21 insertions(+), 28 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 193ba12..87725eb 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -43,22 +43,18 @@ struct scu_regs {
 u32 get_cpu_rev(void)
 {
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-	u32 reg = readl(&anatop->digprog_sololite);
-	u32 type = ((reg >> 16) & 0xff);
-
-	if (type != MXC_CPU_MX6SL) {
-		reg = readl(&anatop->digprog);
-		type = ((reg >> 16) & 0xff);
-		if (type == MXC_CPU_MX6DL) {
-			struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
-			u32 cfg = readl(&scu->config) & 3;
-
-			if (!cfg)
-				type = MXC_CPU_MX6SOLO;
-		}
-	}
-	reg &= 0xff;		/* mx6 silicon revision */
-	return (type << 12) | (reg + 0x10);
+	u32 fsl_system_rev;
+	u32 cpu_rev = readl(&anatop->digprog);
+
+	/* Chip Silicon ID */
+	fsl_system_rev = ((cpu_rev >> 16) & 0xFF) << 12;
+	/* Chip silicon major revision */
+	fsl_system_rev |= ((cpu_rev >> 8) & 0xFF) << 4;
+	fsl_system_rev += 0x10;
+	/* Chip silicon minor revision */
+	fsl_system_rev |= cpu_rev & 0xFF;
+
+	return fsl_system_rev;
 }

 void init_aips(void)
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index a9b86c1..70973c4 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -120,12 +120,10 @@ unsigned imx_ddr_size(void)
 const char *get_imx_type(u32 imxtype)
 {
 	switch (imxtype) {
-	case MXC_CPU_MX6Q:
-		return "6Q";	/* Quad-core version of the mx6 */
-	case MXC_CPU_MX6DL:
-		return "6DL";	/* Dual Lite version of the mx6 */
-	case MXC_CPU_MX6SOLO:
-		return "6SOLO";	/* Solo version of the mx6 */
+	case MXC_CPU_MX6Q_D:
+		return "6Q/D";	/* Quad/Dual version of the mx6 */
+	case MXC_CPU_MX6DL_S:
+		return "6DL/S";	/* Dual-Lite/Solo version of the mx6 */
 	case MXC_CPU_MX6SL:
 		return "6SL";	/* Solo-Lite version of the mx6 */
 	case MXC_CPU_MX51:
diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
index 93ad1c6..1e2a251 100644
--- a/arch/arm/include/asm/arch-mx5/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
@@ -27,9 +27,9 @@
 #define MXC_CPU_MX51		0x51
 #define MXC_CPU_MX53		0x53
 #define MXC_CPU_MX6SL		0x60
-#define MXC_CPU_MX6DL		0x61
-#define MXC_CPU_MX6SOLO		0x62
-#define MXC_CPU_MX6Q		0x63
+#define MXC_CPU_MX6SL		0x60
+#define MXC_CPU_MX6DL_S		0x61
+#define MXC_CPU_MX6Q_D		0x63

 #define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
 u32 get_cpu_rev(void);
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 3193297..9d85340 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -27,9 +27,8 @@
 #define MXC_CPU_MX51		0x51
 #define MXC_CPU_MX53		0x53
 #define MXC_CPU_MX6SL		0x60
-#define MXC_CPU_MX6DL		0x61
-#define MXC_CPU_MX6SOLO		0x62
-#define MXC_CPU_MX6Q		0x63
+#define MXC_CPU_MX6DL_S		0x61
+#define MXC_CPU_MX6Q_D		0x63

 #define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
 u32 get_cpu_rev(void);
--
1.7.9.5