Release 14.7 ngdbuild P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle
ise -dd _ngo -nt timestamp -uc
/home/limb/Documents/fusesoc-builds/build/nexys4/src/nexys4/data/nexys4.ucf -p
xc7a100t-csg324-2 orpsoc_top.ngc orpsoc_top.ngd

Reading NGO file
"/home/limb/Documents/fusesoc-builds/build/nexys4/bld-ise/orpsoc_top.ngc" ...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file
"/home/limb/Documents/fusesoc-builds/build/nexys4/src/nexys4/data/nexys4.ucf"
...
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem:137 - Constraint <NET "sys_clk_pad_i" TNM_NET =
   sys_clk_pin;>
   [/home/limb/Documents/fusesoc-builds/build/nexys4/src/nexys4/data/nexys4.ucf(
   8)]: No appropriate instances for the TNM constraint are driven by
   "sys_clk_pad_i".

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC TS_sys_clk_pin = PERIOD
   sys_clk_pin 100 MHz HIGH 50%;>
   [/home/limb/Documents/fusesoc-builds/build/nexys4/src/nexys4/data/nexys4.ucf(
   9)]: Unable to find an active 'TNM' or 'TimeGrp' constraint named
   'sys_clk_pin'.

WARNING:ConstraintSystem:191 - The TNM 'sys_clk_pin', does not directly or
   indirectly drive any flip-flops, latches and/or RAMS and cannot be actively
   used by the referencing Period constraint 'TS_sys_clk_pin'. If clock manager
   blocks are directly or indirectly driven, a new TNM constraint will not be
   derived even though the referencing constraint is a PERIOD constraint unless
   an output of the clock manager drives flip-flops, latches or RAMs. This TNM
   is used in the following user PERIOD specification:
   <TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100 MHz HIGH 50%;>
   [/home/limb/Documents/fusesoc-builds/build/nexys4/src/nexys4/data/nexys4.ucf(
   9)]

WARNING:ConstraintSystem:197 - The following specification is invalid because
   the referenced TNM constraint was removed:
   <TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100 MHz HIGH 50%;>
   [/home/limb/Documents/fusesoc-builds/build/nexys4/src/nexys4/data/nexys4.ucf(
   9)]

Done...

Checking expanded design ...
WARNING:NgdBuild:486 - Attribute "FACTORY_JF" is not allowed on symbol
   "clkgen0/dcm0" of type "DCM_SP".  This attribute will be ignored.

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   5

Total memory usage is 491268 kilobytes

Writing NGD file "orpsoc_top.ngd" ...
Total REAL time to NGDBUILD completion:  20 sec
Total CPU time to NGDBUILD completion:   20 sec

Writing NGDBUILD log file "orpsoc_top.bld"...