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  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12.  
  13. #include <dt-bindings/gpio/gpio.h>
  14. #include <dt-bindings/input/input.h>
  15.  
  16. / {
  17. aliases {
  18. mxcfb0 = &mxcfb1;
  19. mxcfb1 = &mxcfb2;
  20. mxcfb2 = &mxcfb3;
  21. mxcfb3 = &mxcfb4;
  22. };
  23.  
  24. chosen {
  25. stdout-path = &uart1;
  26. };
  27.  
  28. memory {
  29. reg = <0x10000000 0x40000000>;
  30. };
  31.  
  32. regulators {
  33. compatible = "simple-bus";
  34. #address-cells = <1>;
  35. #size-cells = <0>;
  36.  
  37. reg_usb_otg_vbus: usb-otg-vbus {
  38. compatible = "regulator-fixed";
  39. regulator-name = "usb_otg_vbus";
  40. regulator-min-microvolt = <5000000>;
  41. regulator-max-microvolt = <5000000>;
  42. enable-active-high;
  43. };
  44.  
  45. reg_usb_h1_vbus: usb-h1-vbus {
  46. compatible = "regulator-fixed";
  47. regulator-name = "usb_h1_vbus";
  48. regulator-min-microvolt = <5000000>;
  49. regulator-max-microvolt = <5000000>;
  50. gpio = <&gpio7 12 0>;
  51. pinctrl-names = "default";
  52. pinctrl-0 = <&pinctrl_udoo_usbh1_vbus>;
  53. startup-delay-us = <2>; /* 2 USB2415 requires a POR of 1 us minimum */
  54. enable-active-high;
  55. };
  56.  
  57.  
  58. reg_2p5v: 2p5v {
  59. compatible = "regulator-fixed";
  60. regulator-name = "2P5V";
  61. regulator-min-microvolt = <2500000>;
  62. regulator-max-microvolt = <2500000>;
  63. regulator-always-on;
  64. };
  65.  
  66. reg_3p3v: 3p3v {
  67. compatible = "regulator-fixed";
  68. regulator-name = "3P3V";
  69. regulator-min-microvolt = <3300000>;
  70. regulator-max-microvolt = <3300000>;
  71. regulator-always-on;
  72. };
  73.  
  74. };
  75.  
  76. mxcfb1: fb@0 {
  77. compatible = "fsl,mxc_sdc_fb";
  78. disp_dev = "hdmi";
  79. interface_pix_fmt = "RGB24";
  80. mode_str ="1920x1080M@60";
  81. default_bpp = <24>;
  82. int_clk = <0>;
  83. late_init = <0>;
  84. status = "okay";
  85. };
  86.  
  87. mxcfb2: fb@1 {
  88. compatible = "fsl,mxc_sdc_fb";
  89. disp_dev = "hdmi";
  90. interface_pix_fmt = "RGB24";
  91. mode_str ="1920x1080M@60";
  92. default_bpp = <24>;
  93. int_clk = <0>;
  94. late_init = <0>;
  95. status = "disabled";
  96. };
  97.  
  98. mxcfb3: fb@2 {
  99. compatible = "fsl,mxc_sdc_fb";
  100. disp_dev = "hdmi";
  101. interface_pix_fmt = "RGB24";
  102. mode_str ="1920x1080M@60";
  103. default_bpp = <24>;
  104. int_clk = <0>;
  105. late_init = <0>;
  106. status = "disabled";
  107. };
  108.  
  109. mxcfb4: fb@3 {
  110. compatible = "fsl,mxc_sdc_fb";
  111. disp_dev = "hdmi";
  112. interface_pix_fmt = "RGB24";
  113. mode_str ="1920x1080M@60";
  114. default_bpp = <24>;
  115. int_clk = <0>;
  116. late_init = <0>;
  117. status = "disabled";
  118. };
  119.  
  120. lcd@0 {
  121. compatible = "fsl,lcd";
  122. ipu_id = <0>;
  123. disp_id = <0>;
  124. default_ifmt = "RGB565";
  125. pinctrl-names = "default";
  126. pinctrl-0 = <&pinctrl_ipu1_1>;
  127. status = "disabled";
  128. };
  129.  
  130. lvds_cabc_ctrl {
  131. lvds0-gpios = <&gpio6 15 0>;
  132. lvds1-gpios = <&gpio6 16 0>;
  133. };
  134.  
  135. sound-hdmi {
  136. compatible = "fsl,imx6q-audio-hdmi",
  137. "fsl,imx-audio-hdmi";
  138. model = "imx-audio-hdmi";
  139. hdmi-controller = <&hdmi_audio>;
  140. };
  141.  
  142. sound-spdif {
  143. compatible = "fsl,imx-audio-spdif",
  144. "fsl,imx-sabreauto-spdif";
  145. model = "imx-spdif";
  146. spdif-controller = <&spdif>;
  147. spdif-in;
  148. status = "disabled";
  149. };
  150.  
  151. v4l2_cap_0 {
  152. compatible = "fsl,imx6q-v4l2-capture";
  153. ipu_id = <0>;
  154. csi_id = <0>;
  155. mclk_source = <0>;
  156. status = "okay";
  157. };
  158.  
  159. v4l2_cap_1 {
  160. compatible = "fsl,imx6q-v4l2-capture";
  161. ipu_id = <0>;
  162. csi_id = <1>;
  163. mclk_source = <0>;
  164. status = "okay";
  165. };
  166.  
  167. v4l2_out {
  168. compatible = "fsl,mxc_v4l2_output";
  169. status = "okay";
  170. };
  171. };
  172.  
  173. &audmux {
  174. pinctrl-names = "default";
  175. pinctrl-0 = <&pinctrl_audmux_4>;
  176. status = "okay";
  177. };
  178.  
  179. &ecspi1 {
  180. fsl,spi-num-chipselects = <1>;
  181. cs-gpios = <&gpio3 19 0>;
  182. pinctrl-names = "default";
  183. pinctrl-0 = <&pinctrl_ecspi1_1>;
  184. status = "okay";
  185.  
  186. flash: m25p80@0 {
  187. #address-cells = <1>;
  188. #size-cells = <1>;
  189. compatible = "st,m25p32";
  190. spi-max-frequency = <20000000>;
  191. reg = <0>;
  192. };
  193. };
  194.  
  195. &fec {
  196. pinctrl-names = "default";
  197. pinctrl-0 = <&pinctrl_enet_1>;
  198. driver-can-reset = "no";
  199. phy-mode = "rgmii";
  200. phy-poweron = <&gpio2 31 0>;
  201. phy-reset-gpio = <&gpio3 23 0>;
  202. phy-clk125-en = <&gpio6 24 1>;
  203. phy-mode0 = <&gpio6 29 1>;
  204. phy-mode1 = <&gpio6 28 1>;
  205. phy-mode2 = <&gpio6 27 1>;
  206. phy-mode3 = <&gpio6 25 1>;
  207. status = "okay";
  208. };
  209.  
  210. &i2c1 {
  211. clock-frequency = <100000>;
  212. pinctrl-names = "default";
  213. pinctrl-0 = <&pinctrl_i2c1_2>;
  214. status = "okay";
  215. };
  216.  
  217. &i2c2 {
  218. clock-frequency = <100000>;
  219. pinctrl-names = "default";
  220. pinctrl-0 = <&pinctrl_i2c2_2>;
  221. status = "okay";
  222.  
  223. egalax_ts@04 {
  224. compatible = "eeti,egalax_ts";
  225. reg = <0x04>;
  226. interrupt-parent = <&gpio2>;
  227. interrupts = <28 2>;
  228. wakeup-gpios = <&gpio2 28 0>;
  229. };
  230.  
  231. hdmi: edid@50 {
  232. compatible = "fsl,imx6-hdmi-i2c";
  233. reg = <0x50>;
  234. };
  235. };
  236.  
  237. &i2c3 {
  238. pinctrl-names = "default";
  239. pinctrl-0 = <&pinctrl_i2c3_5>;
  240. status = "okay";
  241. };
  242.  
  243. &iomuxc {
  244. imx6qdl-udoo-usbh1 {
  245. pinctrl_udoo_usbh1: udoo-usbh1 {
  246. fsl,pins = <MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x1b0b0>;
  247. };
  248.  
  249. pinctrl_udoo_usbh1_vbus: udoo-usbh1-vbus {
  250. fsl,pins = <MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000>;
  251. };
  252. };
  253.  
  254. audmux {
  255. pinctrl_audmux_4: audmux-4 {
  256. fsl,pins = <
  257. MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x80000000
  258. MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x80000000
  259. MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x80000000
  260. MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x80000000
  261. >;
  262. };
  263. };
  264.  
  265. ecspi1 {
  266. pinctrl_ecspi1_1: ecspi1grp-1 {
  267. fsl,pins = <
  268. MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
  269. MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
  270. MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
  271. >;
  272. };
  273. };
  274.  
  275. enet {
  276. pinctrl_enet_1: enetgrp-1 {
  277. fsl,pins = <
  278. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  279. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  280. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
  281. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
  282. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
  283. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
  284. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
  285. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  286. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  287. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
  288. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
  289. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
  290. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
  291. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
  292. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  293. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  294. >;
  295. };
  296. };
  297.  
  298. gpmi-nand {
  299. pinctrl_gpmi_nand_1: gpmi-nand-1 {
  300. fsl,pins = <
  301. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  302. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  303. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  304. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  305. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  306. MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
  307. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  308. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  309. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  310. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  311. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  312. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  313. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  314. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  315. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  316. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  317. MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
  318. >;
  319. };
  320. };
  321.  
  322. hdmi_cec {
  323. pinctrl_hdmi_cec_1: hdmicecgrp-1 {
  324. fsl,pins = <
  325. MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
  326. >;
  327. };
  328. };
  329.  
  330. i2c1 {
  331. pinctrl_i2c1_2: i2c1grp-2 {
  332. fsl,pins = <
  333. MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
  334. MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
  335. >;
  336. };
  337. };
  338.  
  339. i2c2 {
  340. pinctrl_i2c2_2: i2c2grp-2 {
  341. fsl,pins = <
  342. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  343. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  344. >;
  345. };
  346. };
  347.  
  348. i2c3 {
  349. pinctrl_i2c3_5: i2c3grp-5 {
  350. fsl,pins = <
  351. MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
  352. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  353. >;
  354. };
  355. };
  356.  
  357. ipu1 {
  358. pinctrl_ipu1_1: ipu1grp-1 {
  359. fsl,pins = <
  360. MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
  361. MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
  362. MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
  363. MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
  364. MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
  365. MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
  366. MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
  367. MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
  368. MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
  369. MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
  370. MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
  371. MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
  372. MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
  373. MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
  374. MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
  375. MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
  376. MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
  377. MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
  378. MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
  379. MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
  380. MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
  381. MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
  382. MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
  383. MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
  384. MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
  385. MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
  386. MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
  387. MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
  388. MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
  389. >;
  390. };
  391. };
  392.  
  393. pwm3 {
  394. pinctrl_pwm3_1: pwm3grp-1 {
  395. fsl,pins = <
  396. MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
  397. >;
  398. };
  399. };
  400.  
  401. spdif {
  402. pinctrl_spdif_1: spdifgrp-1 {
  403. fsl,pins = <
  404. MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
  405. >;
  406. };
  407. };
  408.  
  409. uart2 {
  410. pinctrl_uart2_1: uart2grp-1 {
  411. fsl,pins = <
  412. MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
  413. MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
  414. >;
  415. };
  416. };
  417.  
  418. uart4 {
  419. pinctrl_uart4_1: uart4grp-1 {
  420. fsl,pins = <
  421. MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
  422. MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
  423. >;
  424. };
  425. };
  426.  
  427. usbotg {
  428. pinctrl_usbotg_2: usbotggrp-2 {
  429. fsl,pins = <
  430. MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
  431. >;
  432. };
  433. };
  434.  
  435. usdhc3 {
  436. pinctrl_usdhc3_1: usdhc3grp-1 {
  437. fsl,pins = <
  438. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  439. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  440. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  441. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  442. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  443. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  444. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
  445. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
  446. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
  447. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
  448. >;
  449. };
  450.  
  451. pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */
  452. fsl,pins = <
  453. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9
  454. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9
  455. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9
  456. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9
  457. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B9
  458. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9
  459. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170B9
  460. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170B9
  461. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170B9
  462. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170B9
  463. >;
  464. };
  465.  
  466. pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */
  467. fsl,pins = <
  468. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9
  469. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9
  470. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
  471. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
  472. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
  473. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
  474. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170F9
  475. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170F9
  476. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170F9
  477. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170F9
  478. >;
  479. };
  480.  
  481. pinctrl_usdhc3_2: usdhc3grp-2 {
  482. fsl,pins = <
  483. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  484. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  485. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  486. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  487. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  488. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  489. >;
  490. };
  491. };
  492.  
  493. weim {
  494. pinctrl_weim_cs0_1: weim_cs0grp-1 {
  495. fsl,pins = <
  496. MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
  497. >;
  498. };
  499.  
  500. pinctrl_weim_nor_1: weim_norgrp-1 {
  501. fsl,pins = <
  502. MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
  503. MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
  504. MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
  505. /* data */
  506. MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
  507. MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
  508. MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
  509. MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
  510. MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
  511. MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
  512. MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
  513. MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
  514. MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
  515. MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
  516. MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
  517. MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
  518. MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
  519. MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
  520. MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
  521. MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
  522. /* address */
  523. MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
  524. MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
  525. MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
  526. MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
  527. MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
  528. MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
  529. MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
  530. MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
  531. MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
  532. MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
  533. MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
  534. MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
  535. MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
  536. MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
  537. MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
  538. MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
  539. MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
  540. MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
  541. MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
  542. MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
  543. MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
  544. MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
  545. MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
  546. MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
  547. >;
  548. };
  549. };
  550. };
  551.  
  552. &iomuxc {
  553. pinctrl-names = "default";
  554. pinctrl-0 = <&pinctrl_hog>;
  555.  
  556. imx6qdl-udoo {
  557. pinctrl_hog: hoggrp {
  558. fsl,pins = <
  559. MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x80000000
  560. MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x80000000
  561. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
  562. MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x30B1
  563. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
  564. MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x80000000
  565. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000
  566. MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000
  567. MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x34B1
  568. MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x80000000
  569. MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000
  570. MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
  571. MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000
  572. MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x80000000
  573. MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x80000000
  574. MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000
  575. MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000
  576. MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
  577. MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
  578. MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
  579. MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
  580. MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000
  581. MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000
  582. MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x80000000
  583. MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000
  584. MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x80000000
  585. MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x80000000
  586. MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x80000000
  587. MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x80000000
  588. MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000
  589. MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000
  590. MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x80000000
  591. MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000
  592. MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000
  593. MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x80000000
  594. MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
  595. MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x80000000
  596. MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000
  597. MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000
  598. MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
  599. MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
  600. MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x80000000
  601. MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000
  602. MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000
  603. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000
  604. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000
  605. MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x80000000
  606. MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x80000000
  607. MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x30B1
  608. MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x80000000
  609. MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x80000000
  610. MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x80000000
  611. MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x80000000
  612. MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x80000000
  613. MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x80000000
  614. MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0xB0B1
  615. /*MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000*/
  616. MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x80000000
  617. MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x80000000
  618. MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x80000000
  619. MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x80000000
  620. MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x80000000
  621. MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x80000000
  622. MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x80000000
  623. MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x80000000
  624. MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x80000000
  625. MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x80000000
  626. MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x80000000
  627. MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
  628. MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x80000000
  629. MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x80000000
  630. MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x80000000
  631. MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x80000000
  632. MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x80000000
  633. MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x80000000
  634. MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x80000000
  635. MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x80000000
  636. MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x80000000
  637. MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x80000000
  638. MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x80000000
  639. MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x80000000
  640. MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x80000000
  641. MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x80000000
  642. MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x80000000
  643. MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
  644. /*MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x80000000
  645. MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x80000000*/
  646. /*MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x80000000
  647. MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x80000000
  648. MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x80000000*/
  649. /*MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
  650. MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x80000000*/
  651. MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000
  652. /*MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
  653. MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0*/
  654. >;
  655. };
  656. };
  657. };
  658.  
  659. &pwm3 {
  660. pinctrl-names = "default";
  661. pinctrl-0 = <&pinctrl_pwm3_1>;
  662. status = "disabled";
  663. };
  664.  
  665. &ldb {
  666. ipu_id = <1>;
  667. disp_id = <0>;
  668. ext_ref = <1>;
  669. mode = "sep0";
  670. sec_ipu_id = <1>;
  671. sec_disp_id = <1>;
  672. status = "okay";
  673. };
  674.  
  675. &ssi1 {
  676. fsl,mode = "ac97-slave";
  677. codec-handle = <1>;
  678. ac97-reset = <&gpio2 30 0>;
  679. status = "okay";
  680. };
  681.  
  682. // status = "disabled";
  683. // status = "okay";
  684.  
  685. &uart2 {
  686. pinctrl-names = "default";
  687. pinctrl-0 = <&pinctrl_uart2_1>;
  688. status = "okay";
  689. };
  690.  
  691. &uart4 {
  692. pinctrl-names = "default";
  693. pinctrl-0 = <&pinctrl_uart4_1>;
  694. status = "disabled";
  695. };
  696.  
  697. &spdif {
  698. pinctrl-names = "default";
  699. pinctrl-0 = <&pinctrl_spdif_1>;
  700. status = "disabled";
  701. };
  702.  
  703. &usbh1 {
  704. pinctrl-names = "default";
  705. pinctrl-0 = <&pinctrl_udoo_usbh1>;
  706. vbus-supply = <&reg_usb_h1_vbus>;
  707. /* if I have clk enabled stops booting
  708. clocks = <&clks 201>;
  709. clock-names = "phy";
  710. */
  711. status = "okay";
  712. };
  713.  
  714. &usbotg {
  715. vbus-supply = <&reg_usb_otg_vbus>;
  716. pinctrl-names = "default";
  717. status = "okay";
  718. };
  719. // pinctrl-0 = <&pinctrl_usbotg_2>;
  720.  
  721. &usdhc3 {
  722. pinctrl-names = "default";
  723. pinctrl-0 = <&pinctrl_usdhc3_2>;
  724. non-removable;
  725. status = "okay";
  726. };
  727.  
  728. &usdhc3 {
  729. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  730. pinctrl-0 = <&pinctrl_usdhc3_1>;
  731. pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
  732. pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
  733. cd-gpios = <&gpio7 0 0>;
  734. bus-width = <4>;
  735. keep-power-in-suspend;
  736. enable-sdio-wakeup;
  737. no-1-8-v;
  738. status = "okay";
  739. };
  740.  
  741. &hdmi_core {
  742. ipu_id = <0>;
  743. disp_id = <1>;
  744. status = "okay";
  745. };
  746.  
  747. &hdmi_video {
  748. fsl,phy_reg_vlev = <0x0294>;
  749. fsl,phy_reg_cksymtx = <0x800d>;
  750. status = "okay";
  751. };
  752.  
  753. &hdmi_audio {
  754. status = "okay";
  755. };
  756.  
  757. &hdmi_cec {
  758. pinctrl-names = "default";
  759. pinctrl-0 = <&pinctrl_hdmi_cec_1>;
  760. status = "okay";
  761. };
  762.  
  763. &gpc {
  764. fsl,cpu_pupscr_sw2iso = <0xf>;
  765. fsl,cpu_pupscr_sw = <0xf>;
  766. fsl,cpu_pdnscr_iso2sw = <0x1>;
  767. fsl,cpu_pdnscr_iso = <0x1>;
  768. };
  769.  
  770. &mipi_csi {
  771. status = "okay";
  772. ipu_id = <0>;
  773. csi_id = <1>;
  774. v_channel = <0>;
  775. lanes = <1>;
  776. };
  777.  
  778. &gpmi {
  779. pinctrl-names = "default";
  780. pinctrl-0 = <&pinctrl_gpmi_nand_1>;
  781. status = "disabled"; /* pin conflict with uart3 */
  782. };
  783.  
  784. &weim {
  785. pinctrl-names = "default";
  786. pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
  787. #address-cells = <2>;
  788. #size-cells = <1>;
  789. ranges = <0 0 0x08000000 0x08000000>;
  790. status = "disabled"; /* pin conflict with ecspi1, i2c3 and uart3 */
  791.  
  792. nor@0,0 {
  793. compatible = "cfi-flash";
  794. reg = <0 0 0x02000000>;
  795. #address-cells = <1>;
  796. #size-cells = <1>;
  797. bank-width = <2>;
  798. fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
  799. 0x0000c000 0x1404a38e 0x00000000>;
  800. };
  801. };
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