lab4.1

module syncROM ( output reg [4:0] z , input [9:0] d , input clock);

( * synthesis , rom_block = "ROM CELLXYZ01" * )

reg [4:0] mem [9:0];

initial \$readmemb("sqrt.data",mem);
always @ ( posedge clock )
begin
    z = mem[d];
end

endmodule