----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    21:08:22 04/19/2014
-- Design Name:
-- Module Name:    SevenSegment - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SevenSegment is
    Port ( clk : in  STD_LOGIC;			--t9 clock
           IN0 : in std_logic_vector (3 downto 0);
           IN1 : in std_logic_vector (3 downto 0);
           IN2 : in std_logic_vector (3 downto 0);
           IN3 : in std_logic_vector (3 downto 0);
           AN0 : out  STD_LOGIC;
           AN1 : out  STD_LOGIC;
           AN2 : out  STD_LOGIC;
           AN3 : out  STD_LOGIC;
           DP  : out  STD_LOGIC;
           SEVEN : out std_logic_vector(6 downto 0));
end SevenSegment;

architecture Behavioral of SevenSegment is

	Signal zero : std_logic_vector(6 downto 0):= "1000000";
	Signal one : std_logic_vector(6 downto 0):= "1111001";
	Signal two : std_logic_vector(6 downto 0):= "0100100";
	Signal three : std_logic_vector(6 downto 0):= "0110000";
	Signal four : std_logic_vector(6 downto 0):= "0011001";
	Signal five : std_logic_vector(6 downto 0):= "0010010";
	Signal six : std_logic_vector(6 downto 0):= "0000010";
	Signal seven7 : std_logic_vector(6 downto 0):= "1111000";
	Signal eight : std_logic_vector(6 downto 0):= "0000000";
	Signal nine : std_logic_vector(6 downto 0):= "0010000";

	Signal counter : integer range 0 to 1023:=0;
	Signal currentSeg : integer range 0 to 3:=0;

	Signal seg : std_logic_vector(6 downto 0):= "0000000";

	Signal selectSeg : std_logic_vector(3 downto 0):= "1111";

begin
	process(clk)
	begin
		if(clk'event AND clk='1') then
			counter<=counter+1;
			if(counter=1023) then
				counter<=0;
				currentSeg<=currentSeg+1;
			end if;
		end if;

		case currentSeg is
			when 0 =>
				selectSeg<="0111"; --least significant bit  xxx0
				case IN0 is
					when "0000" =>
						seg<=zero;
					when "0001" =>
						seg<=one;
					when "0010" =>
						seg<=two;
					when "0011" =>
						seg<=three;
					when "0100" =>
						seg<=four;
					when "0101" =>
						seg<=five;
					when "0110" =>
						seg<=six;
					when "0111" =>
						seg<=seven7;
					when "1000" =>
						seg<=eight;
					when "1001" =>
						seg<=nine;
					when others => seg <=zero;
				end case;
			when 1 =>
				selectSeg<="1011";
				case IN1 is
					when "0000" =>
						seg<=zero;
					when "0001" =>
						seg<=one;
					when "0010" =>
						seg<=two;
					when "0011" =>
						seg<=three;
					when "0100" =>
						seg<=four;
					when "0101" =>
						seg<=five;
					when "0110" =>
						seg<=six;
					when "0111" =>
						seg<=seven7;
					when "1000" =>
						seg<=eight;
					when "1001" =>
						seg<=nine;
					when others => seg <=zero;
				end case;
				when 2 =>
				selectSeg<="1101";
				case IN2 is
					when "0000" =>
						seg<=zero;
					when "0001" =>
						seg<=one;
					when "0010" =>
						seg<=two;
					when "0011" =>
						seg<=three;
					when "0100" =>
						seg<=four;
					when "0101" =>
						seg<=five;
					when "0110" =>
						seg<=six;
					when "0111" =>
						seg<=seven7;
					when "1000" =>
						seg<=eight;
					when "1001" =>
						seg<=nine;
					when others => seg <=zero;
				end case;
				when 3 =>
				selectSeg<="1110";
				case IN3 is
					when "0000" =>
						seg<=zero;
					when "0001" =>
						seg<=one;
					when "0010" =>
						seg<=two;
					when "0011" =>
						seg<=three;
					when "0100" =>
						seg<=four;
					when "0101" =>
						seg<=five;
					when "0110" =>
						seg<=six;
					when "0111" =>
						seg<=seven7;
					when "1000" =>
						seg<=eight;
					when "1001" =>
						seg<=nine;
					when others => seg <=zero;
				end case;
			when others => currentSeg <=0;
		end case;

		AN0<=selectSeg(0);
		AN1<=selectSeg(1);
		AN2<=selectSeg(2);
		AN3<=selectSeg(3);

		SEVEN<=seg;
	end process;
end Behavioral;