AVR Timer0 CTC mode

/***********************************************************************
 *  timi-main.c
 *  ATmega16A timer handling C and assembly training
 *  by tovis 2015
***********************************************************************/
#include  <avr/io.h>
#include  <avr/interrupt.h>

//----------------------------------------------------------------------
#define F_CPU           16000000ul      // ATmega16A external crystal 16MHz

//----------------------------------------------------------------------
#define PERIOD_10MS     10
#define PERIOD_100MS    100
#define PERIOD_1S       1000

//----------------------------------------------------------------------
volatile uint16_t       tick_counter;

//----------------------------------------------------------------------
int             main(void)
{
    uint8_t     aux;
  uint16_t  tmr0;
    //... code ...
  DDRA   = 0xFF;                        // whole PORTA set as output
  TCCR0  = 0x1B;                        // Timer0 CTC mode:
                                        // using internal clock,
                                        // prescaler 1/64, toggle OC0
  OCR0   = 250;                         // Set compare register for 1ms
  TIFR   = 0;                           // Clear pending interrupts
  // Enable timer 0 compare match interrupt
  TIMSK |= (1 << OCIE0);
  TIMSK |= _BV(OCIE0);
  /*
    It's not so good. Why not using SBI?
    TIMSK |= (1 << OCIE0);
    ca: 89 b7           in  r24, 0x39   ; 57
    cc: 82 60           ori r24, 0x02   ; 2
    ce: 89 bf           out 0x39, r24   ; 57
    TIMSK |= _BV(OCIE0);
    d0: 89 b7           in  r24, 0x39   ; 57
    d2: 82 60           ori r24, 0x02   ; 2
    d4: 89 bf           out 0x39, r24   ; 57
  */
  DDRB  |= (1 << 3);                    // ??? set PORTB, OC0 pin to output
  sei();                                // Enbale all interrupts
  //---
  tmr0 = 0;
  while ( 1 )                           // Loop forever
  {
    toggle_A0();
    if ( tick_counter >= tmr0 )
    {
      TIMSK = (1 << OCIE0);             // Enable timer 0 compare match interrupt
      tmr0 = tick_counter + PERIOD_10MS;
      // tmr0 = tick_counter + PERIOD_100MS;
      // tmr0 = tick_counter + PERIOD_1S;
      toggle_A2();
    }
  }
} //end main

/***********************************************************************
 *  end timi-main.c
***********************************************************************/

/***********************************************************************
 *  timi.S
 *  ATmega16A timer handling C and assembly training
 *  by tovis 2015
***********************************************************************/
#include  <avr/io.h>

.extern tick_counter

//----------------------------------------------------------------------
.global TIMER0_COMP_vect
TIMER0_COMP_vect:
        RCALL   toggle_A1
        PUSH    R16
        IN      R16, _SFR_IO_ADDR(SREG)
        PUSH    R16
//------
        LDS     R24, (tick_counter)
        LDS     R25, (tick_counter) + 1
        ADIW    R24, 0x0001
        STS     tick_counter, R24
        STS     tick_counter+1, R25
//------
        POP     R16
        OUT     _SFR_IO_ADDR(SREG), R16
        POP     R16
        RETI
//**********************************************************************
.global toggle_A0
toggle_A0:
        SBIC    _SFR_IO_ADDR(PINA),  0
        CBI     _SFR_IO_ADDR(PORTA), 0
        SBIS    _SFR_IO_ADDR(PINA),  0
        SBI     _SFR_IO_ADDR(PORTA), 0
        RET
//----------------------------------------------------------------------
.global toggle_A1
toggle_A1:
        SBIC    _SFR_IO_ADDR(PINA),  1
        CBI     _SFR_IO_ADDR(PORTA), 1
        SBIS    _SFR_IO_ADDR(PINA),  1
        SBI     _SFR_IO_ADDR(PORTA), 1
        RET
//----------------------------------------------------------------------
.global toggle_A2
toggle_A2:
        SBIC    _SFR_IO_ADDR(PINA),  2
        CBI     _SFR_IO_ADDR(PORTA), 2
        SBIS    _SFR_IO_ADDR(PINA),  2
        SBI     _SFR_IO_ADDR(PORTA), 2
        RET
/***********************************************************************
 *  end timi.S
***********************************************************************/