le Code

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-- Entity: Lec11
-- Date: Feb 8, 2012
-- Author:
--
-- Description
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity controller is
    port(
        clock        : in  std_logic;
        reset        : in  std_logic;
        loada, loadb : out std_logic;
        muxs         : out std_logic_vector(1 downto 0);
        alus         : out std_logic_vector(2 downto 0)
    );
end entity controller;

architecture RTL of controller is
    type states is (s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16);
    signal q, d : states;
begin
    FF : process(clock, reset) is
    begin
        if reset = '0' then
            q <= s1;
        elsif rising_edge(clock) then
            q <= d;
        end if;
    end process FF;

    with q select d <=
        s2 when s1,
        s3 when s2,
        s4 when s3,
        s5 when s4,
        s6 when s5,
        s7 when s6,
        s8 when s7,
        s9 when s8,
        s10 when s9,
        s11 when s10,
        s12 when s11,
        s13 when s12,
        s14 when s13,
        s15 when s14,
        s16 when others;

    with q select loada <=
        '1' when s1,                    -- load 0
        '0' when s2,                    -- hold
        '0' when s3,                    -- hold
        '0' when s4,                    -- load 2y
        '0' when s5,                    -- hold
        '0' when s6,                    -- hold
        '1' when s7,                    -- load x
        '0' when s8,                    -- hold
        '0' when s9,                    -- hold
        '0' when s10,                   -- hold
        '0' when s11,                   -- hold
        '0' when s12,                   -- hold
        '0' when s13,                   -- hold
        '0' when s14,                   -- hold
        '0' when s15,                   -- hold
        '0' when s16;                   -- hold


    with q select loadb <=
        '0' when s1,                    -- hold
        '1' when s2,                    -- load y
        '1' when s3,                    -- load 2y
        '0' when s4,                    -- hold
        '1' when s5,                    -- load !2y
        '1' when s6,                    -- load -2y
        '0' when s7,                    -- hold
        '1' when s8,                    -- load x - 2y
        '1' when s9,                    -- load 2x - 2y
        '1' when s10,                   -- load 3x - 2y
        '1' when s11,                   -- load 4x - 2y
        '1' when s12,                   -- load 5x - 2y
        '1' when s13,                   -- load 6x - 2y
        '1' when s14,                   -- load 7x - 2y
        '1' when s15,                   -- load 8x - 2y
        '0' when s16;                   -- hold


    with q select alus <=
        x"0" when s1,                   -- 0 - > a        = 0
        x"0" when s2,                   -- y -> b
        x"0" when s3,                   -- b + b -> b     = 2y
        x"0" when s4,                   -- a or b -> a    = 2y
        x"0" when s5,                   -- a nand b -> b  = !2y
        x"0" when s6,                   -- b + 1 -> b     = -2y
        x"0" when s7,                   -- x -> a
        x"0" when s8,                   -- x + b -> b     = x -2y
        x"0" when s9,                   -- x + b -> b     = 2x -2y
        x"0" when s10,                  -- x + b -> b     = 3x -2y
        x"0" when s11,                  -- x + b -> b     = 4x -2y
        x"0" when s12,                  -- x + b -> b     = 5x -2y
        x"0" when s13,                  -- x + b -> b     = 6x -2y
        x"0" when s14,                  -- x + b -> b     = 7x -2y
        x"0" when s15,                  -- x + b -> b     = 8x -2y
        x"0" when s16;                  -- hold


    with q select muxs <=
        x"3" when s1,                   -- alu
        x"1" when s2,                   -- y
        x"3" when s3,                   -- alu
        x"3" when s4,                   -- alu
        x"3" when s5,                   -- alu
        x"3" when s6,                   -- alu
        x"0" when s7,                   -- x
        x"3" when s8,                   -- alu
        x"3" when s9,                   -- alu
        x"3" when s10,                  -- alu
        x"3" when s11,                  -- alu
        x"3" when s12,                  -- alu
        x"3" when s13,                  -- alu
        x"3" when s14,                  -- alu
        x"3" when s15,                  -- alu
        x"2" when s16;                  -- hold


end architecture RTL;