broken clockport 2 ftdi fifo

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity clockportFifo is
    Port(
        data :      inout STD_LOGIC_VECTOR (7 downto 0);
        addressIn : in STD_LOGIC_VECTOR (3 downto 0);
        iord :      in STD_LOGIC;
        iowr :      in STD_LOGIC;
        cs :        in STD_LOGIC;

        fifoData :  inout STD_LOGIC_VECTOR (7 downto 0);
        fifoRxE :   in STD_LOGIC;
        fifoTxE :   in STD_LOGIC;
        fifoWr :    out STD_LOGIC;
        fifoRd :    out STD_LOGIC;
        fifoSlp :   in STD_LOGIC);
end clockportFifo;

architecture Behavioral of clockportFifo is
    signal address : STD_LOGIC_VECTOR (3 downto 0);
    signal cpRead : STD_LOGIC;
    signal cpWrite : STD_LOGIC;

    signal ctrlReg : STD_LOGIC_VECTOR (7 downto 0);
    signal ctrlFifoWr : STD_LOGIC := '1';
    signal ctrlFifoRd : STD_LOGIC := '1';
    signal dataTmp : STD_LOGIC_VECTOR (7 downto 0);
begin

    cpRead <= '0' when cs = '0' and iord = '0' else '1';
    cpWrite <= '0' when cs = '0' and iowr = '0' else '1';
    address <= addressIn when cs = '0' and (iord = '0' or iowr = '0');

    ctrlReg <= "0" & ctrlFifoRd & "000" & fifoRxE & fifoTxE & fifoSlp;

    fifoRd <= ctrlFifoRd;

    process (cpRead, address)
    begin
        ctrlFifoRd <= '1';
        if cpRead = '0' and address = "0000" then
            data <= "00000000";
        elsif cpRead = '0' and address = "0001" then
            data <= ctrlReg;
        elsif cpRead = '0' and address = "0010" and fifoRxE = '0' and ctrlFifoRd = '0' then
            ctrlFifoRd <= '0';
            data <= fifoData;
        else
            data <= "ZZZZZZZZ";
        end if;
    end process;

    process (cpWrite, address)
    begin
        fifoData <= "ZZZZZZZZ";
        fifoWr <= '1';
        if cpWrite = '0' and address = "0001" then
            ctrlFifoRd <= data(6);
        elsif cpWrite = '0' and address = "0010" then
            fifoWr <= '0';
            fifoData <= data;
        end if;
    end process;

end Behavioral;