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- 300MHz
- Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=8 Size=2048MB
- OUT
- BUILD=====5
- F:32 1061 2 0 40
- GetRemapTbl flag = 0
- OK! 49729
- unsigned!
- SecureBootEn = 0 0
- Boot ver: 2013-05-18#1.20
- start_linux=====61316
- 715275 Starting kernel...@0x60408000
- [ 0.000000] Initializing cgroup subsys cpu
- [ 0.000000] Linux version 3.0.36omegamoon+ (uprinz@BigBox) (gcc version 4.4.3 (GCC) ) #1 SMP PREEMPT Sun Jun 30 00:29:00 CEST 2013
- [ 0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
- [ 0.000000] CPU: VIPT nonaliasing data cache, VIPT aliasing instruction cache
- [ 0.000000] Machine: RK30board
- [ 0.000000] memory reserve: Memory(base:0x91800000 size:80M) reserved for <ion>
- [ 0.000000] memory reserve: Memory(base:0x90d00000 size:11M) reserved for <fb0 buf>
- [ 0.000000] memory reserve: Total reserved 91M
- [ 0.000000] Memory policy: ECC disabled, Data cache writeback
- [ 0.000000] bootconsole [earlycon0] enabled
- [ 0.000000] CPU SRAM: copied sram code from c0bca000 to fef00100 - fef022d0
- [ 0.000000] CPU SRAM: copied sram data from c0bcc1d0 to fef022d0 - fef02a4c
- [ 0.000000] sram_log: 4q ?& : 4q ?) !?, # 0q *! ! 3q @ 3q
- [ 0.000000] CLKDATA_MSG: pll_flag = 0x00
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable ddr_pll with 300000000
- [ 0.000000] clk_enable ddr with 300000000
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable arm_pll with 600000000
- [ 0.000000] clk_enable cpu_div with 18750000
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable general_pll with 891000000
- [ 0.000000] clk_enable cpu_gpll_path with 891000000
- [ 0.000000] clk_enable arm_pll with 600000000
- [ 0.000000] clk_enable core with 600000000
- [ 0.000000] clk_enable l2c with 600000000
- [ 0.000000] clk_enable core with 600000000
- [ 0.000000] clk_enable core_dbg with 600000000
- [ 0.000000] clk_enable core with 600000000
- [ 0.000000] clk_enable core_periph with 150000000
- [ 0.000000] clk_enable core with 600000000
- [ 0.000000] clk_enable aclk_core with 300000000
- [ 0.000000] clk_enable cpu_div with 18750000
- [ 0.000000] clk_enable aclk_cpu with 18750000
- [ 0.000000] clk_enable pclk_cpu with 9375000
- [ 0.000000] clk_enable atclk_cpu with 9375000
- [ 0.000000] clk_enable aclk_cpu with 18750000
- [ 0.000000] clk_enable hclk_cpu with 18750000
- [ 0.000000] clk_enable ahb2apb with 9375000
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable uart2 with 24000000
- [ 0.000000] clk_enable general_pll with 891000000
- [ 0.000000] clk_enable aclk_periph with 27843750
- [ 0.000000] clk_enable pclk_periph with 13921875
- [ 0.000000] clk_enable pclk_uart2 with 13921875
- [ 0.000000] clk_enable aclk_cpu with 18750000
- [ 0.000000] clk_enable dma1 with 18750000
- [ 0.000000] clk_enable aclk_cpu with 18750000
- [ 0.000000] clk_enable intmem with 18750000
- [ 0.000000] clk_enable aclk_cpu with 18750000
- [ 0.000000] clk_enable aclk_strc_sys with 18750000
- [ 0.000000] clk_enable hclk_cpu with 18750000
- [ 0.000000] clk_enable rom with 18750000
- [ 0.000000] clk_enable hclk_cpu with 18750000
- [ 0.000000] clk_enable hclk_cpubus with 18750000
- [ 0.000000] clk_enable hclk_cpu with 18750000
- [ 0.000000] clk_enable hclk_ahb2apb with 18750000
- [ 0.000000] clk_enable hclk_cpu with 18750000
- [ 0.000000] clk_enable hclk_vio_bus with 18750000
- [ 0.000000] clk_enable hclk_cpu with 18750000
- [ 0.000000] clk_enable hclk_imem0 with 18750000
- [ 0.000000] clk_enable hclk_cpu with 18750000
- [ 0.000000] clk_enable hclk_imem1 with 18750000
- [ 0.000000] clk_enable pclk_cpu with 9375000
- [ 0.000000] clk_enable tzpc with 9375000
- [ 0.000000] clk_enable pclk_cpu with 9375000
- [ 0.000000] clk_enable pclk_ddrupctl with 9375000
- [ 0.000000] clk_enable pclk_cpu with 9375000
- [ 0.000000] clk_enable pclk_ddrpubl with 9375000
- [ 0.000000] clk_enable pclk_cpu with 9375000
- [ 0.000000] clk_enable dbg with 9375000
- [ 0.000000] clk_enable pclk_cpu with 9375000
- [ 0.000000] clk_enable grf with 9375000
- [ 0.000000] clk_enable pclk_cpu with 9375000
- [ 0.000000] clk_enable pmu with 9375000
- [ 0.000000] clk_enable aclk_periph with 27843750
- [ 0.000000] clk_enable dma2 with 27843750
- [ 0.000000] clk_enable aclk_periph with 27843750
- [ 0.000000] clk_enable aclk_smc with 27843750
- [ 0.000000] clk_enable aclk_periph with 27843750
- [ 0.000000] clk_enable aclk_peri_niu with 27843750
- [ 0.000000] clk_enable aclk_periph with 27843750
- [ 0.000000] clk_enable aclk_cpu_peri with 27843750
- [ 0.000000] clk_enable aclk_periph with 27843750
- [ 0.000000] clk_enable aclk_peri_axi_matrix with 27843750
- [ 0.000000] clk_enable aclk_periph with 27843750
- [ 0.000000] clk_enable hclk_periph with 27843750
- [ 0.000000] clk_enable hclk_peri_axi_matrix with 27843750
- [ 0.000000] clk_enable hclk_periph with 27843750
- [ 0.000000] clk_enable hclk_peri_ahb_arbi with 27843750
- [ 0.000000] clk_enable hclk_periph with 27843750
- [ 0.000000] clk_enable hclk_emem_peri with 27843750
- [ 0.000000] clk_enable hclk_periph with 27843750
- [ 0.000000] clk_enable nandc with 27843750
- [ 0.000000] clk_enable hclk_periph with 27843750
- [ 0.000000] clk_enable hclk_usb_peri with 27843750
- [ 0.000000] clk_enable pclk_periph with 13921875
- [ 0.000000] clk_enable pclk_peri_axi_matrix with 13921875
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] L310 cache controller enabled
- [ 0.000000] l2x0: 16 ways, CACHE_ID 0x4100c0c8, AUX_CTRL 0x76050001, Cache size: 524288 B
- [ 0.000000] DDR DEBUG: version 1.00 20130427
- [ 0.000000] DDR DEBUG: DDR3 Device
- [ 0.000000] DDR DEBUG: Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Total Capability=2048MB
- [ 0.000000] DDR DEBUG: init success!!! freq=396MHz
- [ 0.000000] DDR DEBUG: DTONE=0x1, DTERR=0x0, DTIERR=0x0, DTPASS=0x4, DGSL=1 extra clock, DGPS=90
- [ 0.000000] DDR DEBUG: DTONE=0x1, DTERR=0x0, DTIERR=0x0, DTPASS=0x4, DGSL=1 extra clock, DGPS=90
- [ 0.000000] DDR DEBUG: DTONE=0x1, DTERR=0x0, DTIERR=0x0, DTPASS=0x4, DGSL=1 extra clock, DGPS=90
- [ 0.000000] DDR DEBUG: DTONE=0x1, DTERR=0x0, DTIERR=0x0, DTPASS=0x4, DGSL=1 extra clock, DGPS=90
- [ 0.000000] DDR DEBUG: ZERR=0, ZDONE=0, ZPD=0x0, ZPU=0x0, OPD=0x0, OPU=0x0
- [ 0.000000] DDR DEBUG: DRV Pull-Up=0xb, DRV Pull-Dwn=0xb
- [ 0.000000] DDR DEBUG: ODT Pull-Up=0x2, ODT Pull-Dwn=0x2
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable aclk_lcdc1_pre with 297000000
- [ 0.000000] clk_enable aclk_vio1 with 297000000
- [ 0.000000] clk_enable aclk_rga with 297000000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable aclk_lcdc1_pre with 297000000
- [ 0.000000] clk_enable aclk_vio1 with 297000000
- [ 0.000000] clk_enable aclk_lcdc1 with 297000000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable aclk_lcdc1_pre with 297000000
- [ 0.000000] clk_enable aclk_vio1 with 297000000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable aclk_lcdc0_pre with 297000000
- [ 0.000000] clk_enable aclk_vio0 with 297000000
- [ 0.000000] clk_enable aclk_ipp with 297000000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable aclk_lcdc0_pre with 297000000
- [ 0.000000] clk_enable aclk_vio0 with 297000000
- [ 0.000000] clk_enable aclk_cif0 with 297000000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable aclk_lcdc0_pre with 297000000
- [ 0.000000] clk_enable aclk_vio0 with 297000000
- [ 0.000000] clk_enable aclk_lcdc0 with 297000000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable aclk_lcdc0_pre with 297000000
- [ 0.000000] clk_enable aclk_vio0 with 297000000
- [ 0.000000] clk_enable pclk_periph with 74250000
- [ 0.000000] clk_enable pclk_saradc with 74250000
- [ 0.000000] clk_enable pclk_periph with 74250000
- [ 0.000000] clk_enable gpio3 with 74250000
- [ 0.000000] clk_enable pclk_periph with 74250000
- [ 0.000000] clk_enable i2c4 with 74250000
- [ 0.000000] clk_enable pclk_periph with 74250000
- [ 0.000000] clk_enable i2c3 with 74250000
- [ 0.000000] clk_enable pclk_periph with 74250000
- [ 0.000000] clk_enable i2c2 with 74250000
- [ 0.000000] clk_enable pclk_periph with 74250000
- [ 0.000000] clk_enable pclk_uart3 with 74250000
- [ 0.000000] clk_enable pclk_periph with 74250000
- [ 0.000000] clk_enable pclk_spi1 with 74250000
- [ 0.000000] clk_enable pclk_periph with 74250000
- [ 0.000000] clk_enable pclk_spi0 with 74250000
- [ 0.000000] clk_enable pclk_periph with 74250000
- [ 0.000000] clk_enable wdt with 74250000
- [ 0.000000] clk_enable pclk_periph with 74250000
- [ 0.000000] clk_enable pwm23 with 74250000
- [ 0.000000] clk_enable hclk_periph with 148500000
- [ 0.000000] clk_enable hclk_emmc with 148500000
- [ 0.000000] clk_enable hclk_periph with 148500000
- [ 0.000000] clk_enable hclk_sdio with 148500000
- [ 0.000000] clk_enable hclk_periph with 148500000
- [ 0.000000] clk_enable hclk_sdmmc with 148500000
- [ 0.000000] clk_enable hclk_periph with 148500000
- [ 0.000000] clk_enable hclk_pidfilter with 148500000
- [ 0.000000] clk_enable hclk_periph with 148500000
- [ 0.000000] clk_enable hclk_hsadc with 148500000
- [ 0.000000] clk_enable hclk_periph with 148500000
- [ 0.000000] clk_enable hclk_hsic with 148500000
- [ 0.000000] clk_enable hclk_usb_peri with 148500000
- [ 0.000000] clk_enable hclk_otg1 with 148500000
- [ 0.000000] clk_enable hclk_usb_peri with 148500000
- [ 0.000000] clk_enable hclk_otg0 with 148500000
- [ 0.000000] clk_enable hclk_periph with 148500000
- [ 0.000000] clk_enable hclk_mac with 148500000
- [ 0.000000] clk_enable aclk_periph with 148500000
- [ 0.000000] clk_enable aclk_gps with 148500000
- [ 0.000000] clk_enable ahb2apb with 74250000
- [ 0.000000] clk_enable pclk_uart1 with 74250000
- [ 0.000000] clk_enable ahb2apb with 74250000
- [ 0.000000] clk_enable pclk_uart0 with 74250000
- [ 0.000000] clk_enable pclk_cpu with 74250000
- [ 0.000000] clk_enable efuse with 74250000
- [ 0.000000] clk_enable pclk_cpu with 74250000
- [ 0.000000] clk_enable gpio2 with 74250000
- [ 0.000000] clk_enable pclk_cpu with 74250000
- [ 0.000000] clk_enable gpio1 with 74250000
- [ 0.000000] clk_enable pclk_cpu with 74250000
- [ 0.000000] clk_enable gpio0 with 74250000
- [ 0.000000] clk_enable pclk_cpu with 74250000
- [ 0.000000] clk_enable i2c1 with 74250000
- [ 0.000000] clk_enable pclk_cpu with 74250000
- [ 0.000000] clk_enable i2c0 with 74250000
- [ 0.000000] clk_enable pclk_cpu with 74250000
- [ 0.000000] clk_enable pclk_timer2 with 74250000
- [ 0.000000] clk_enable pclk_cpu with 74250000
- [ 0.000000] clk_enable pclk_timer0 with 74250000
- [ 0.000000] clk_enable pclk_cpu with 74250000
- [ 0.000000] clk_enable pwm01 with 74250000
- [ 0.000000] clk_enable hclk_cpu with 148500000
- [ 0.000000] clk_enable hclk_rga with 148500000
- [ 0.000000] clk_enable hclk_cpu with 148500000
- [ 0.000000] clk_enable hclk_ipp with 148500000
- [ 0.000000] clk_enable hclk_cpu with 148500000
- [ 0.000000] clk_enable hclk_cif0 with 148500000
- [ 0.000000] clk_enable hclk_cpu with 148500000
- [ 0.000000] clk_enable hclk_lcdc1 with 148500000
- [ 0.000000] clk_enable hclk_cpu with 148500000
- [ 0.000000] clk_enable hclk_lcdc0 with 148500000
- [ 0.000000] clk_enable hclk_cpu with 148500000
- [ 0.000000] clk_enable hclk_spdif with 148500000
- [ 0.000000] clk_enable hclk_cpu with 148500000
- [ 0.000000] clk_enable hclk_i2s0_2ch with 148500000
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable timer6 with 24000000
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable timer5 with 24000000
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable timer4 with 24000000
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable timer3 with 24000000
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable timer2 with 24000000
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable timer1 with 24000000
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable timer0 with 24000000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable uart_pll with 594000000
- [ 0.000000] clk_enable uart3_div with 49500000
- [ 0.000000] clk_enable uart3_frac_div with 2475000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable uart_pll with 594000000
- [ 0.000000] clk_enable uart3_div with 49500000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable uart_pll with 594000000
- [ 0.000000] clk_enable uart2_div with 49500000
- [ 0.000000] clk_enable uart2_frac_div with 2475000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable uart_pll with 594000000
- [ 0.000000] clk_enable uart2_div with 49500000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable uart_pll with 594000000
- [ 0.000000] clk_enable uart1_div with 49500000
- [ 0.000000] clk_enable uart1_frac_div with 2475000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable uart_pll with 594000000
- [ 0.000000] clk_enable uart1_div with 49500000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable uart_pll with 594000000
- [ 0.000000] clk_enable uart0_div with 49500000
- [ 0.000000] clk_enable uart0_frac_div with 2475000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable uart_pll with 594000000
- [ 0.000000] clk_enable uart0_div with 49500000
- [ 0.000000] clk_enable hclk_periph with 148500000
- [ 0.000000] clk_enable emmc with 37125000
- [ 0.000000] clk_enable hclk_periph with 148500000
- [ 0.000000] clk_enable sdio with 24750000
- [ 0.000000] clk_enable hclk_periph with 148500000
- [ 0.000000] clk_enable sdmmc with 24750000
- [ 0.000000] clk_enable pclk_periph with 74250000
- [ 0.000000] clk_enable spi1 with 74250000
- [ 0.000000] clk_enable pclk_periph with 74250000
- [ 0.000000] clk_enable spi0 with 74250000
- [ 0.000000] clk_enable hclk_periph with 148500000
- [ 0.000000] clk_enable smc with 148500000
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable saradc with 93750
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable hsadc_pll_div with 2320312
- [ 0.000000] clk_enable hsadc_frac_div with 116015
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable hsadc_pll_div with 2320312
- [ 0.000000] clk_enable ddr_pll with 396000000
- [ 0.000000] clk_enable mac_pll_div with 33000000
- [ 0.000000] clk_enable mac_ref with 33000000
- [ 0.000000] clk_enable mii_tx with 33000000
- [ 0.000000] clk_enable ddr_pll with 396000000
- [ 0.000000] clk_enable mac_pll_div with 33000000
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable otgphy1 with 24000000
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable otgphy0 with 24000000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable i2s_pll with 594000000
- [ 0.000000] clk_enable spdif_div with 9281250
- [ 0.000000] clk_enable spdif_frac_div with 464062
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable i2s_pll with 594000000
- [ 0.000000] clk_enable spdif_div with 9281250
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable i2s_pll with 594000000
- [ 0.000000] clk_enable i2s0_div with 9281250
- [ 0.000000] clk_enable i2s0_frac_div with 0
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable i2s_pll with 594000000
- [ 0.000000] clk_enable i2s0_div with 9281250
- [ 0.000000] clk_enable pclkin_cif0 with 0
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable cif_out_pll with 594000000
- [ 0.000000] clk_enable cif0_out_div with 18562500
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable dclk_lcdc1 with 2320312
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable dclk_lcdc0 with 2320312
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable aclk_lcdc1_pre with 297000000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable aclk_lcdc0_pre with 297000000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable aclk_vdpu with 297000000
- [ 0.000000] clk_enable hclk_vdpu with 74250000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable aclk_vdpu with 297000000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable aclk_vepu with 297000000
- [ 0.000000] clk_enable hclk_vepu with 74250000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable aclk_vepu with 297000000
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable codec_pll with 798000000
- [ 0.000000] clk_enable aclk_gpu with 199500000
- [ 0.000000] clk_enable general_pll with 594000000
- [ 0.000000] clk_enable ddr_gpll_path with 594000000
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable codec_pll with 798000000
- [ 0.000000] PERCPU: Embedded 7 pages/cpu @c313f000 s7008 r8192 d13472 u32768
- [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 496896
- [ 0.000000] Kernel command line: console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init initrd=0x62000000,0x00130000 mtdparts=rk29xxnand:0x00002000@0x00002000(misc),0x00006000@0x00004000(kernel),0x00008000@0x0000A000(boot),0x00010000@0x00012000(recovery),0x00020000@0x00022000(backup),0x00040000@0x00042000(cache),0x00400000@0x00082000(userdata),0x00002000@0x00482000(kpanic),0x00100000@0x00484000(system),-@0x00584000(user) bootver=2013-05-18#1.20 firmware_ver=4.1.1
- [ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
- [ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
- [ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
- [ 0.000000] Memory: 781MB 1176MB = 1957MB total
- [ 0.000000] Memory: 1966496k/1966496k available, 130656k reserved, 1204224K highmem
- [ 0.000000] Virtual kernel memory layout:
- [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
- [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
- [ 0.000000] DMA : 0xffc00000 - 0xffe00000 ( 2 MB)
- [ 0.000000] vmalloc : 0xf7000000 - 0xfe800000 ( 120 MB)
- [ 0.000000] lowmem : 0xc0000000 - 0xf6800000 ( 872 MB)
- [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
- [ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
- [ 0.000000] .init : 0xc0408000 - 0xc0512000 (1064 kB)
- [ 0.000000] .text : 0xc0512000 - 0xc0b605f4 (6458 kB)
- [ 0.000000] .data : 0xc0b62000 - 0xc0bc98a8 ( 415 kB)
- [ 0.000000] .bss : 0xc0bcd024 - 0xc1672a50 (10903 kB)
- [ 0.000000] SLUB: Genslabs=13, HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
- [ 0.000000] Preemptible hierarchical RCU implementation.
- [ 0.000000] NR_IRQS:352
- [ 0.000000] clk_enable pclk_cpu with 74250000
- [ 0.000000] clk_enable gpio0 with 74250000
- [ 0.000000] clk_enable pclk_cpu with 74250000
- [ 0.000000] clk_enable gpio1 with 74250000
- [ 0.000000] clk_enable pclk_cpu with 74250000
- [ 0.000000] clk_enable gpio2 with 74250000
- [ 0.000000] clk_enable pclk_periph with 74250000
- [ 0.000000] clk_enable gpio3 with 74250000
- [ 0.000000] rk30_gpio_init: 128 gpio irqs in 4 banks
- [ 0.000000] clk_enable pclk_cpu with 74250000
- [ 0.000000] clk_enable pclk_timer0 with 74250000
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable timer0 with 24000000
- [ 0.000000] clk_enable pclk_timer0 with 74250000
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable timer1 with 24000000
- [ 0.000000] clk_enable pclk_timer0 with 74250000
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable timer4 with 24000000
- [ 0.000000] clk_enable pclk_timer0 with 74250000
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable timer5 with 24000000
- [ 0.000000] clk_enable pclk_timer0 with 74250000
- [ 0.000000] clk_enable xin24m with 24000000
- [ 0.000000] clk_enable timer6 with 24000000
- [ 0.000000] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956ms
- [ 0.000000] rk_timer: version 1.2
- [ 0.000000] Console: colour dummy device 80x30
- [ 0.008622] Calibrating delay loop (skipped) preset value.. 1631.46 BogoMIPS (lpj=8157341)
- [ 0.017645] pid_max: default: 32768 minimum: 301
- [ 0.022923] Mount-cache hash table entries: 512
- [ 0.028475] Initializing cgroup subsys debug
- [ 0.033187] Initializing cgroup subsys cpuacct
- [ 0.038142] Initializing cgroup subsys freezer
- [ 0.043059] CPU: Testing write buffer coherency: ok
- [ 0.129082] CPU1: Booted secondary processor
- [ 0.169078] CPU2: Booted secondary processor
- [ 0.209079] CPU3: Booted secondary processor
- [ 0.209118] Brought up 4 CPUs
- [ 0.226592] SMP: Total of 4 processors activated (6525.87 BogoMIPS).
- [ 0.233900] devtmpfs: initialized
- [ 0.243747] NET: Registered protocol family 16
- [ 0.248720] last_log: 0xf0900000 map to 0xf7004000 and copy to 0xc0bd1180 (version 2.1)
- [ 0.271121] warning:lcdc0 not add to system!
- [ 0.275900] lcdc1 is used as primary display device controller!
- [ 0.282673] rk29sdk_wifi_bt_gpio_control_init: request wifi power gpio failed
- <hit enter to activate fiq debugger>
- 0.291939] console [ttyFIQ0] enabled, bootconsole disabled
- [ 0.291939] console [ttyFIQ0] enabled, bootconsole disabled
- [ 0.300988] Registered FIQ tty driver f083dcc0
- [ 0.314348] bio: create slab <bio-0> at 0
- [ 0.318786] SCSI subsystem initialized
- [ 0.319015] usbcore: registered new interface driver usbfs
- [ 0.319138] usbcore: registered new interface driver hub
- [ 0.333360] usbcore: registered new device driver usb
- [ 0.333504] clk_enable pclk_cpu with 74250000
- [ 0.333536] clk_enable i2c0 with 74250000
- [ 0.333663] rk30_i2c rk30_i2c.0: i2c-0: RK30 I2C adapter
- [ 0.333721] clk_enable pclk_cpu with 74250000
- [ 0.333752] clk_enable i2c1 with 74250000
- [ 0.333960] rk30_i2c rk30_i2c.1: i2c-1: RK30 I2C adapter
- [ 0.334020] clk_enable pclk_periph with 74250000
- [ 0.334051] clk_enable i2c2 with 74250000
- [ 0.334226] rk30_i2c rk30_i2c.2: i2c-2: RK30 I2C adapter
- [ 0.334286] clk_enable pclk_periph with 74250000
- [ 0.334317] clk_enable i2c3 with 74250000
- [ 0.334421] rk30_i2c rk30_i2c.3: i2c-3: RK30 I2C adapter
- [ 0.334480] clk_enable pclk_periph with 74250000
- [ 0.334511] clk_enable i2c4 with 74250000
- [ 0.334614] rk30_i2c rk30_i2c.4: i2c-4: RK30 I2C adapter
- [ 0.407299] clk_enable pclk_periph with 74250000
- [ 0.407335] clk_enable pclk_saradc with 74250000
- [ 0.407386] clk_enable xin24m with 24000000
- [ 0.407415] clk_enable saradc with 1000000
- [ 0.407455] rk30-adc rk30-adc: rk30 adc: driver initialized
- [ 0.407742] Advanced Linux Sound Architecture Driver Version 1.0.24.
- [ 0.408185] Bluetooth: Core ver 2.16
- [ 0.408253] NET: Registered protocol family 31
- [ 0.408285] Bluetooth: HCI device and connection manager initialized
- [ 0.408329] Bluetooth: HCI socket layer initialized
- [ 0.408363] Bluetooth: L2CAP socket layer initialized
- [ 0.408410] Bluetooth: SCO socket layer initialized
- [ 0.409481] rk fb probe ok!
- [ 0.409577] clk_enable i2c1 with 74250000
- [ 0.409852] i2c i2c-1: No ack, Maybe slave(addr: 0x5a) not exist or abnormal power-on, retry 2...
- [ 0.409909] clk_enable i2c1 with 74250000
- [ 0.410177] i2c i2c-1: No ack, Maybe slave(addr: 0x5a) not exist or abnormal power-on, retry 1...
- [ 0.410232] clk_enable i2c1 with 74250000
- [ 0.410498] i2c i2c-1: No ack, Maybe slave(addr: 0x5a) not exist or abnormal power-on, retry 0...
- [ 0.410553] The device is not act8846
- [ 0.410612] i2c-core: driver [act8846] using legacy suspend method
- [ 0.410652] i2c-core: driver [act8846] using legacy resume method
- [ 0.410712] Switching to clocksource rk_timer
- [ 0.417539] lcdc1:reg_phy_base = 0x1010e000,reg_vir_base:0xf70a0000
- [ 0.417609] fb0:win0
- [ 0.417614] fb1:win1
- [ 0.417619] fb2:win2
- [ 0.417692] clk_enable hclk_cpu with 148500000
- [ 0.417722] clk_enable hclk_lcdc1 with 148500000
- [ 0.417754] clk_enable general_pll with 594000000
- [ 0.417785] clk_enable dclk_lcdc1 with 2320312
- [ 0.417816] clk_enable general_pll with 594000000
- [ 0.417847] clk_enable aclk_lcdc1_pre with 297000000
- [ 0.417879] clk_enable aclk_vio1 with 297000000
- [ 0.417909] clk_enable aclk_lcdc1 with 297000000
- [ 0.417945] clk_enable pd_vio with 0
- [ 0.417969] clk_enable pd_lcdc1 with 0
- [ 0.417995] rk3188 lcdc1 clk enable...
- [ 0.418038] rk3188 lcdc1 clk disable...
- [ 0.418073] lcdc1: dclk:74250000>>fps:60
- [ 0.418104] rk30-lcdc rk30-lcdc.1: rk3188_load_screen for lcdc1 ok!
- [ 0.418606] Switched to NOHz mode on CPU #0
- [ 0.419113] Switched to NOHz mode on CPU #3
- [ 0.419129] Switched to NOHz mode on CPU #1
- [ 0.419144] Switched to NOHz mode on CPU #2
- [ 0.440346] fb0:phy:90d00000>>vir:f8000000>>len:0xb00000
- [ 0.440689] rk_fb_register>>>>>fb0
- [ 0.440897] rk_fb_register>>>>>fb1
- [ 0.440927] clk_enable hclk_cpu with 148500000
- [ 0.440957] clk_enable hclk_lcdc1 with 148500000
- [ 0.440988] clk_enable general_pll with 594000000
- [ 0.441019] clk_enable dclk_lcdc1 with 74250000
- [ 0.441050] clk_enable general_pll with 594000000
- [ 0.441081] clk_enable aclk_lcdc1_pre with 297000000
- [ 0.441113] clk_enable aclk_vio1 with 297000000
- [ 0.441142] clk_enable aclk_lcdc1 with 297000000
- [ 0.441184] clk_enable pd_vio with 0
- [ 0.441208] clk_enable pd_lcdc1 with 0
- [ 0.441234] rk3188 lcdc1 clk enable...
- [ 0.441260] lcdc1 wakeup from standby!
- [ 0.441287] lcdc1 win0 open,atv layer:1
- [ 0.441322] lcdc1>>win0_set_par>>format:2>>>xact:1280>>yact:720>>xsize:1280>>ysize:720>>xvir:1280>>yvir:720>>xpos:260>>ypos:25>>
- [ 0.460462] lcdc1>>win0_display:y_addr:0x90d00000>>uv_addr:0x0
- [ 0.460507] rk3188 lcdc1 probe ok!
- [ 0.460648] HDMI: hdmi_register() - video source 1 display 0
- [ 0.460932] HDMI: hdmi_submit_work event 0100 delay 0
- [ 0.461067] HDMI:
- [ 0.461073] hdmi_work_queue() - evt= 1 0
- [ 0.461111] HDMI: hdmi_work_queue() - exit
- [ 0.461120]
- [ 0.461268] clk_enable i2c2 with 74250000
- [ 0.461754] clk_enable i2c2 with 74250000
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