module part3 (SW, LEDR, HEX0, HEX1, HEX4, HEX6);

	input [7:0] SW; //A is SW[7:4] and B is SW[3:0]
	output [7:0] LEDR;
	output [6:0] HEX0, HEX1, HEX4, HEX6;

	//sevenseq(a, b, c, d, H)
	sevenseg i0(SW[7], SW[6], SW[5], SW[4], HEX6);
	sevenseg i1(SW[3], SW[2], SW[1], SW[0], HEX4);

	assign LEDR = SW;

	wire [3:0] w0, w1, w2, w3, w4, w5, w6;
	wire c0, c1, c2;

	//multand (      a,     b,  f);
	multand m0(SW[7:4], SW[0], w0);
	multand m1(SW[7:4], SW[1], w1);
	multand m2(SW[7:4], SW[2], w2);
	multand m3(SW[7:4], SW[3], w3);

	//n_bit_adder				( S,Cout,              A,  B,  Cin);
	n_bit_adder #(4) ripple0(w4, c0, {1'b0, w0[3:1]}, w1, 1'b0);
	n_bit_adder #(4) ripple1(w5, c1, {c0,   w4[3:1]}, w2, 1'b0);
	n_bit_adder #(4) ripple2(w6, c2, {c1,   w5[3:1]}, w3, 1'b0);

//	//alun(s, a, b, cin, f, ovrflw)
//	alun a0(3'b011, {1'b0, w0[3:1]}, w1, 1'b0, w4, c0);
//	alun a1(3'b011, {c0, w4[3:1]}, w2, 1'b0, w5, c1);
//	alun a2(3'b011, {c1, w5[3:1]}, w3, 1'b0, w6, c2);

	//sevenseq(a, b, c, d, H)
	sevenseg s0(w6[0], w5[0], w4[0], w0[0], HEX0);
	sevenseg s1(c2, w6[3], w6[2], w6[1], HEX1);

endmodule


module n_bit_adder(S, Cout, A, B, Cin);
	parameter n = 4;

	input Cin;
	input [n-1: 0] A, B;

	output reg [n-1: 0] S;
	output reg Cout;

	always @(A, B, Cin)
		{Cout, S} = A + B + Cin;

endmodule