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-- Company:
-- Engineer:
--
-- Create Date:    21:37:28 11/19/2014
-- Design Name:
-- Module Name:    stope - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity stope is
    Port ( iCLK : in  STD_LOGIC;
           inRST : in  STD_LOGIC;
           inSTART : in  STD_LOGIC;
           inSTOP : in  STD_LOGIC;
           inCONTINUE : in  STD_LOGIC;
           oSEC : out  STD_LOGIC_VECTOR (7 downto 0));
end stope;

architecture Behavioral of stope is
		signal sTC : std_logic := '0';
		signal sR : std_logic := '0';
		signal sREG1 : std_logic_vector(24 downto 0) := (others => '0');
		signal sREG2 : std_logic_vector(7 downto 0) := (others => '0');
begin
		process(iCLK, inRST) begin
			if(inRST = '0') then
                sR <= '0';
			elsif(iCLK'event and iCLK = '1') then
				if(inSTOP = '0') then
                sR <= '0';
				elsif(inSTART = '0') then
                sR <= '1';
				elsif(inCONTINUE = '0') then
                sR <= '1';
				end if;
			end if;
		end process;

		process(iCLK, inRST) begin

        if(inRST = '0') then
                sREG1 <= "0000000000000000000000000";
        elsif(iCLK'event and iCLK = '1') then
					if(inSTART = '0') then
						sREG1 <= "0000000000000000000000000";
                elsif(sR = '1') then
                        if(sREG1 = "1011011100011010111111111") then           --ovaj binarni =23 999 999
                                sTC <= '1';
                                sREG1 <= "0000000000000000000000000";
                        else
                                sREG1 <= sREG1+1;
                                sTC <= '0';
                        end if;
                end if;
        end if;
		end process;

		process(iCLK, inRST) begin
        if(inRST = '0') then
                sREG2 <= "00000000";
        elsif(iCLK'event and iCLK = '1') then
					 if(inSTART = '0') then
							sREG2 <= "00000000";
                elsif(sR = '1') then
                     sREG2 <= sREG2+("0000000" & sTC);
                end if;
        end if;
		end process;

		oSEC <= sREG2;

end Behavioral;