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  1. /*
  2. * Intel ACPI Component Architecture
  3. * AML Disassembler version 20140210-00 [Feb 10 2014]
  4. * Copyright (c) 2000 - 2014 Intel Corporation
  5. *
  6. * Original Table Header:
  7. * Signature "SSDT"
  8. * Length 0x0000036A (874)
  9. * Revision 0x01
  10. * Checksum 0x00
  11. * OEM ID "APPLE "
  12. * OEM Table ID "CpuPm"
  13. * OEM Revision 0x00013600 (79360)
  14. * Compiler ID "INTL"
  15. * Compiler Version 0x20140210 (538182160)
  16. */
  17.  
  18. DefinitionBlock ("ssdt.aml", "SSDT", 1, "APPLE ", "CpuPm", 0x00013600)
  19. {
  20. External (\_PR_.CPU0, DeviceObj)
  21. External (\_PR_.CPU1, DeviceObj)
  22. External (\_PR_.CPU2, DeviceObj)
  23. External (\_PR_.CPU3, DeviceObj)
  24.  
  25. Scope (\_PR_.CPU0)
  26. {
  27. Method (_INI, 0, NotSerialized)
  28. {
  29. Store ("ssdtPRGen version....: 13.6 / Mac OS X 10.9.4 (13E28)", Debug)
  30. Store ("target processor.....: i7-3667U", Debug)
  31. Store ("running processor....: Intel(R) Core(TM) i7-3667U CPU @ 2.00GHz", Debug)
  32. Store ("baseFrequency........: 800", Debug)
  33. Store ("frequency............: 2000", Debug)
  34. Store ("busFrequency.........: 100", Debug)
  35. Store ("logicalCPUs..........: 4", Debug)
  36. Store ("maximum TDP..........: 17", Debug)
  37. Store ("packageLength........: 25", Debug)
  38. Store ("turboStates..........: 12", Debug)
  39. Store ("maxTurboFrequency....: 3200", Debug)
  40. Store ("machdep.xcpm.mode....: 0", Debug)
  41. }
  42.  
  43. Name (APLF, Zero)
  44. Name (APSN, 0x0C)
  45. Name (APSS, Package (0x19)
  46. {
  47. /* High Frequency Modes (turbo) */
  48. Package (0x06) { 0x0C80, 0x004268, 0x0A, 0x0A, 0x2000, 0x2000 },
  49. Package (0x06) { 0x0C1C, 0x004268, 0x0A, 0x0A, 0x1F00, 0x1F00 },
  50. Package (0x06) { 0x0BB8, 0x004268, 0x0A, 0x0A, 0x1E00, 0x1E00 },
  51. Package (0x06) { 0x0B54, 0x004268, 0x0A, 0x0A, 0x1D00, 0x1D00 },
  52. Package (0x06) { 0x0AF0, 0x004268, 0x0A, 0x0A, 0x1C00, 0x1C00 },
  53. Package (0x06) { 0x0A8C, 0x004268, 0x0A, 0x0A, 0x1B00, 0x1B00 },
  54. Package (0x06) { 0x0A28, 0x004268, 0x0A, 0x0A, 0x1A00, 0x1A00 },
  55. Package (0x06) { 0x09C4, 0x004268, 0x0A, 0x0A, 0x1900, 0x1900 },
  56. Package (0x06) { 0x0960, 0x004268, 0x0A, 0x0A, 0x1800, 0x1800 },
  57. Package (0x06) { 0x08FC, 0x004268, 0x0A, 0x0A, 0x1700, 0x1700 },
  58. Package (0x06) { 0x0898, 0x004268, 0x0A, 0x0A, 0x1600, 0x1600 },
  59. Package (0x06) { 0x0834, 0x004268, 0x0A, 0x0A, 0x1500, 0x1500 },
  60. /* High Frequency Modes (non-turbo) */
  61. Package (0x06) { 0x07D0, 0x004268, 0x0A, 0x0A, 0x1400, 0x1400 },
  62. Package (0x06) { 0x076C, 0x003E5E, 0x0A, 0x0A, 0x1300, 0x1300 },
  63. Package (0x06) { 0x0708, 0x003A6A, 0x0A, 0x0A, 0x1200, 0x1200 },
  64. Package (0x06) { 0x06A4, 0x003689, 0x0A, 0x0A, 0x1100, 0x1100 },
  65. Package (0x06) { 0x0640, 0x0032BC, 0x0A, 0x0A, 0x1000, 0x1000 },
  66. Package (0x06) { 0x05DC, 0x002F03, 0x0A, 0x0A, 0x0F00, 0x0F00 },
  67. Package (0x06) { 0x0578, 0x002B5E, 0x0A, 0x0A, 0x0E00, 0x0E00 },
  68. Package (0x06) { 0x0514, 0x0027CC, 0x0A, 0x0A, 0x0D00, 0x0D00 },
  69. Package (0x06) { 0x04B0, 0x00244D, 0x0A, 0x0A, 0x0C00, 0x0C00 },
  70. Package (0x06) { 0x044C, 0x0020E2, 0x0A, 0x0A, 0x0B00, 0x0B00 },
  71. Package (0x06) { 0x03E8, 0x001D89, 0x0A, 0x0A, 0x0A00, 0x0A00 },
  72. Package (0x06) { 0x0384, 0x001A43, 0x0A, 0x0A, 0x0900, 0x0900 },
  73. /* Low Frequency Mode */
  74. Package (0x06) { 0x0320, 0x001710, 0x0A, 0x0A, 0x0800, 0x0800 }
  75. })
  76.  
  77. Method (ACST, 0, NotSerialized)
  78. {
  79. Store ("Method CPU0.ACST Called", Debug)
  80. Store ("CPU0 C-States : 29", Debug)
  81.  
  82. /* Low Power Modes for CPU0 */
  83. Return (Package (0x06)
  84. {
  85. One,
  86. 0x04,
  87. Package (0x04)
  88. {
  89. ResourceTemplate ()
  90. {
  91. Register (FFixedHW,
  92. 0x01, // Bit Width
  93. 0x02, // Bit Offset
  94. 0x0000000000000000, // Address
  95. 0x01, // Access Size
  96. )
  97. },
  98. One,
  99. Zero,
  100. 0x03E8
  101. },
  102.  
  103. Package (0x04)
  104. {
  105. ResourceTemplate ()
  106. {
  107. Register (FFixedHW,
  108. 0x01, // Bit Width
  109. 0x02, // Bit Offset
  110. 0x0000000000000010, // Address
  111. 0x03, // Access Size
  112. )
  113. },
  114. 0x03,
  115. 0xCD,
  116. 0x01F4
  117. },
  118.  
  119. Package (0x04)
  120. {
  121. ResourceTemplate ()
  122. {
  123. Register (FFixedHW,
  124. 0x01, // Bit Width
  125. 0x02, // Bit Offset
  126. 0x0000000000000020, // Address
  127. 0x03, // Access Size
  128. )
  129. },
  130. 0x06,
  131. 0xF5,
  132. 0x015E
  133. },
  134.  
  135. Package (0x04)
  136. {
  137. ResourceTemplate ()
  138. {
  139. Register (FFixedHW,
  140. 0x01, // Bit Width
  141. 0x02, // Bit Offset
  142. 0x0000000000000030, // Address
  143. 0x03, // Access Size
  144. )
  145. },
  146. 0x07,
  147. 0xF5,
  148. 0xC8
  149. }
  150. })
  151. }
  152.  
  153. Method (_DSM, 4, NotSerialized)
  154. {
  155. Store ("Method CPU0._DSM Called", Debug)
  156.  
  157. If (LEqual (Arg2, Zero))
  158. {
  159. Return (Buffer (One)
  160. {
  161. 0x03
  162. })
  163. }
  164.  
  165. Return (Package (0x02)
  166. {
  167. "plugin-type",
  168. One
  169. })
  170. }
  171. }
  172.  
  173. Scope (\_PR_.CPU1)
  174. {
  175. Method (APSS, 0, NotSerialized)
  176. {
  177. Store ("Method _PR_.CPU1.APSS Called", Debug)
  178.  
  179. Return (\_PR_.CPU0.APSS)
  180. }
  181.  
  182. Method (ACST, 0, NotSerialized)
  183. {
  184. Store ("Method CPU1.ACST Called", Debug)
  185. Store ("CPU1 C-States : 7", Debug)
  186.  
  187. /* Low Power Modes for CPU1 */
  188. Return (Package (0x05)
  189. {
  190. One,
  191. 0x03,
  192. Package (0x04)
  193. {
  194. ResourceTemplate ()
  195. {
  196. Register (FFixedHW,
  197. 0x01, // Bit Width
  198. 0x02, // Bit Offset
  199. 0x0000000000000000, // Address
  200. 0x01, // Access Size
  201. )
  202. },
  203. One,
  204. 0x03E8,
  205. 0x03E8
  206. },
  207.  
  208. Package (0x04)
  209. {
  210. ResourceTemplate ()
  211. {
  212. Register (FFixedHW,
  213. 0x01, // Bit Width
  214. 0x02, // Bit Offset
  215. 0x0000000000000010, // Address
  216. 0x03, // Access Size
  217. )
  218. },
  219. 0x02,
  220. 0x94,
  221. 0x01F4
  222. },
  223.  
  224. Package (0x04)
  225. {
  226. ResourceTemplate ()
  227. {
  228. Register (FFixedHW,
  229. 0x01, // Bit Width
  230. 0x02, // Bit Offset
  231. 0x0000000000000030, // Address
  232. 0x03, // Access Size
  233. )
  234. },
  235. 0x03,
  236. 0xC6,
  237. 0xC8
  238. }
  239. })
  240. }
  241. }
  242.  
  243. Scope (\_PR_.CPU2)
  244. {
  245. Method (APSS, 0, NotSerialized)
  246. {
  247. Store ("Method _PR_.CPU2.APSS Called", Debug)
  248.  
  249. Return (\_PR_.CPU0.APSS)
  250. }
  251.  
  252. Method (ACST, 0, NotSerialized) { Return (\_PR_.CPU1.ACST ()) }
  253. }
  254.  
  255. Scope (\_PR_.CPU3)
  256. {
  257. Method (APSS, 0, NotSerialized)
  258. {
  259. Store ("Method _PR_.CPU3.APSS Called", Debug)
  260.  
  261. Return (\_PR_.CPU0.APSS)
  262. }
  263.  
  264. Method (ACST, 0, NotSerialized) { Return (\_PR_.CPU1.ACST ()) }
  265. }
  266. }
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