#define SCR_HIU 0x100b
#define HPG_TIMER 0x100f
#define HARM_ASB_MB0 0x1030
#define HARM_ASB_MB1 0x1031
#define HARM_ASB_MB2 0x1032
#define HARM_ASB_MB3 0x1033
#define HASB_ARM_MB0 0x1034
#define HASB_ARM_MB1 0x1035
#define HASB_ARM_MB2 0x1036
#define HASB_ARM_MB3 0x1037
#define HHI_TIMER90K 0x103b
#define HHI_MEM_PD_REG0 0x1040
#define HHI_VPU_MEM_PD_REG0 0x1041
#define HHI_VPU_MEM_PD_REG1 0x1042
#define HHI_AUD_DAC_CTRL 0x1044
#define HHI_VIID_CLK_DIV 0x104a
#define HHI_VIID_CLK_CNTL 0x104b
#define HHI_VIID_DIVIDER_CNTL 0x104c
#define HHI_GCLK_MPEG0 0x1050
#define HHI_GCLK_MPEG1 0x1051
#define HHI_GCLK_MPEG2 0x1052
#define HHI_GCLK_OTHER 0x1054
#define HHI_GCLK_AO 0x1055
#define HHI_SYS_CPU_CLK_CNTL1 0x1057
#define HHI_VID_CLK_DIV 0x1059
#define HHI_MPEG_CLK_CNTL 0x105d
#define HHI_AUD_CLK_CNTL 0x105e
#define HHI_VID_CLK_CNTL 0x105f
#define HHI_WIFI_CLK_CNTL 0x1060
#define HHI_WIFI_PLL_CNTL 0x1061
#define HHI_WIFI_PLL_CNTL2 0x1062
#define HHI_WIFI_PLL_CNTL3 0x1063
#define HHI_AUD_CLK_CNTL2 0x1064
#define HHI_VID_CLK_CNTL2 0x1065
#define HHI_VID_DIVIDER_CNTL 0x1066
#define HHI_SYS_CPU_CLK_CNTL 0x1067
#define HHI_MALI_CLK_CNTL 0x106c
#define HHI_MIPI_PHY_CLK_CNTL 0x106e
#define HHI_VPU_CLK_CNTL 0x106f
#define HHI_OTHER_PLL_CNTL 0x1070
#define HHI_OTHER_PLL_CNTL2 0x1071
#define HHI_OTHER_PLL_CNTL3 0x1072
#define HHI_HDMI_CLK_CNTL 0x1073
#define HHI_DEMOD_CLK_CNTL 0x1074
#define HHI_SATA_CLK_CNTL 0x1075
#define HHI_ETH_CLK_CNTL 0x1076
#define HHI_CLK_DOUBLE_CNTL 0x1077
#define HHI_VDEC_CLK_CNTL 0x1078
#define HHI_VDEC2_CLK_CNTL 0x1079
#define HHI_VDEC3_CLK_CNTL 0x107a
#define HHI_EDP_APB_CLK_CNTL 0x107b
#define HHI_VDEC4_CLK_CNTL 0x107b
#define HHI_HDMI_PLL_CNTL 0x107c
#define HHI_HDMI_PLL_CNTL1 0x107d
#define HHI_HDMI_PLL_CNTL2 0x107e
#define HHI_HDMI_AFC_CNTL 0x107f
#define HHI_HDMIRX_CLK_CNTL 0x1080
#define HHI_HDMIRX_AUD_CLK_CNTL 0x1081
#define HHI_VID_PLL_MOD_CNTL0 0x1084
#define HHI_VID_PLL_MOD_LOW_TCNT 0x1085
#define HHI_VID_PLL_MOD_HIGH_TCNT 0x1086
#define HHI_VID_PLL_MOD_NOM_TCNT 0x1087
#define HHI_USB_CLK_CNTL 0x1089
#define HHI_GEN_CLK_CNTL 0x108a
#define HHI_GEN_CLK_CNTL2 0x108b
#define HHI_JTAG_CONFIG 0x108e
#define HHI_VAFE_CLKXTALIN_CNTL 0x108f
#define HHI_VAFE_CLKOSCIN_CNTL 0x1090
#define HHI_VAFE_CLKIN_CNTL 0x1091
#define HHI_TVFE_AUTOMODE_CLK_CNTL 0x1092
#define HHI_VAFE_CLKPI_CNTL 0x1093
#define HHI_VDIN_MEAS_CLK_CNTL 0x1094
#define HHI_PCM_CLK_CNTL 0x1096
#define HHI_NAND_CLK_CNTL 0x1097
#define HHI_ISP_LED_CLK_CNTL 0x1098
#define HHI_EDP_TX_PHY_CNTL0 0x109c
#define HHI_EDP_TX_PHY_CNTL1 0x109d
#define HHI_MPLL_CNTL 0x10a0
#define HHI_MPLL_CNTL2 0x10a1
#define HHI_MPLL_CNTL3 0x10a2
#define HHI_MPLL_CNTL4 0x10a3
#define HHI_MPLL_CNTL5 0x10a4
#define HHI_MPLL_CNTL6 0x10a5
#define HHI_MPLL_CNTL7 0x10a6
#define HHI_MPLL_CNTL8 0x10a7
#define HHI_MPLL_CNTL9 0x10a8
#define HHI_MPLL_CNTL10 0x10a9
#define HHI_ADC_PLL_CNTL 0x10aa
#define HHI_ADC_PLL_CNTL2 0x10ab
#define HHI_ADC_PLL_CNTL3 0x10ac
#define HHI_ADC_PLL_CNTL4 0x10ad
#define HHI_ADC_PLL_CNTL5 0x10ae
#define HHI_ADC_PLL_CNTL6 0x10af
#define HHI_AUDCLK_PLL_CNTL 0x10b0
#define HHI_AUDCLK_PLL_CNTL2 0x10b1
#define HHI_AUDCLK_PLL_CNTL3 0x10b2
#define HHI_AUDCLK_PLL_CNTL4 0x10b3
#define HHI_AUDCLK_PLL_CNTL5 0x10b4
#define HHI_AUDCLK_PLL_CNTL6 0x10b5
#define HHI_L2_DDR_CLK_CNTL 0x10b6
#define HHI_VDAC_CNTL0 0x10bd
#define HHI_VDAC_CNTL1 0x10be
#define HHI_SYS_PLL_CNTL 0x10c0
#define HHI_SYS_PLL_CNTL2 0x10c1
#define HHI_SYS_PLL_CNTL3 0x10c2
#define HHI_SYS_PLL_CNTL4 0x10c3
#define HHI_SYS_PLL_CNTL5 0x10c4
#define HHI_DPLL_TOP_0 0x10c6
#define HHI_DPLL_TOP_1 0x10c7
#define HHI_VID_PLL_CNTL 0x10c8
#define HHI_VID_PLL_CNTL2 0x10c9
#define HHI_VID_PLL_CNTL3 0x10ca
#define HHI_VID_PLL_CNTL4 0x10cb
#define HHI_VID_PLL_CNTL5 0x10cc
#define HHI_VID_PLL_CNTL6 0x10cd
#define HHI_DSI_LVDS_EDP_CNTL0 0x10d1
#define HHI_DSI_LVDS_EDP_CNTL1 0x10d2
#define HHI_CSI_PHY_CNTL0 0x10d3
#define HHI_CSI_PHY_CNTL1 0x10d4
#define HHI_CSI_PHY_CNTL2 0x10d5
#define HHI_CSI_PHY_CNTL3 0x10d6
#define HHI_CSI_PHY_CNTL4 0x10d7
#define HHI_DIF_CSI_PHY_CNTL0 0x10d8
#define HHI_DIF_CSI_PHY_CNTL1 0x10d9
#define HHI_DIF_CSI_PHY_CNTL2 0x10da
#define HHI_DIF_CSI_PHY_CNTL3 0x10db
#define HHI_DIF_CSI_PHY_CNTL4 0x10dc
#define HHI_DIF_CSI_PHY_CNTL5 0x10dd
#define HHI_LVDS_TX_PHY_CNTL0 0x10de
#define HHI_LVDS_TX_PHY_CNTL1 0x10df
#define HHI_VID2_PLL_CNTL 0x10e0
#define HHI_VID2_PLL_CNTL2 0x10e1
#define HHI_VID2_PLL_CNTL3 0x10e2
#define HHI_VID2_PLL_CNTL4 0x10e3
#define HHI_VID2_PLL_CNTL5 0x10e4
#define HHI_VID2_PLL_CNTL6 0x10e5
#define HHI_HDMI_PHY_CNTL0 0x10e8
#define HHI_HDMI_PHY_CNTL1 0x10e9
#define HHI_HDMI_PHY_CNTL2 0x10ea
#define VERSION_CTRL 0x1100
#define RESET0_REGISTER 0x1101
#define RESET1_REGISTER 0x1102
#define RESET2_REGISTER 0x1103
#define RESET3_REGISTER 0x1104
#define RESET4_REGISTER 0x1105
#define RESET5_REGISTER 0x1106
#define RESET6_REGISTER 0x1107
#define RESET7_REGISTER 0x1108
#define RESET0_MASK 0x1110
#define RESET1_MASK 0x1111
#define RESET2_MASK 0x1112
#define RESET3_MASK 0x1113
#define RESET4_MASK 0x1114
#define RESET5_MASK 0x1115
#define RESET6_MASK 0x1116
#define CRT_MASK 0x1117
#define RESET7_MASK 0x1118
#define RESET0_LEVEL 0x1120
#define RESET1_LEVEL 0x1121
#define RESET2_LEVEL 0x1122
#define RESET3_LEVEL 0x1123
#define RESET4_LEVEL 0x1124
#define RESET5_LEVEL 0x1125
#define RESET6_LEVEL 0x1126
#define RESET7_LEVEL 0x1127
#define DVIN_FRONT_END_CTRL 0x12e0
#define DVIN_HS_LEAD_VS_ODD 0x12e1
#define DVIN_ACTIVE_START_PIX 0x12e2
#define DVIN_ACTIVE_START_LINE 0x12e3
#define DVIN_DISPLAY_SIZE 0x12e4
#define DVIN_CTRL_STAT 0x12e5
#define AIU_958_BPF 0x1500
#define AIU_958_BRST 0x1501
#define AIU_958_LENGTH 0x1502
#define AIU_958_PADDSIZE 0x1503
#define AIU_958_MISC 0x1504
#define AIU_958_FORCE_LEFT 0x1505
#define AIU_958_DISCARD_NUM 0x1506
#define AIU_958_DCU_FF_CTRL 0x1507
#define AIU_958_CHSTAT_L0 0x1508
#define AIU_958_CHSTAT_L1 0x1509
#define AIU_958_CTRL 0x150a
#define AIU_958_RPT 0x150b
#define AIU_I2S_MUTE_SWAP 0x150c
#define AIU_I2S_SOURCE_DESC 0x150d
#define AIU_I2S_MED_CTRL 0x150e
#define AIU_I2S_MED_THRESH 0x150f
#define AIU_I2S_DAC_CFG 0x1510
#define AIU_I2S_SYNC 0x1511
#define AIU_I2S_MISC 0x1512
#define AIU_I2S_OUT_CFG 0x1513
#define AIU_I2S_FF_CTRL 0x1514
#define AIU_RST_SOFT 0x1515
#define AIU_CLK_CTRL 0x1516
#define AIU_MIX_ADCCFG 0x1517
#define AIU_MIX_CTRL 0x1518
#define AIU_CLK_CTRL_MORE 0x1519
#define AIU_958_POP 0x151a
#define AIU_MIX_GAIN 0x151b
#define AIU_958_SYNWORD1 0x151c
#define AIU_958_SYNWORD2 0x151d
#define AIU_958_SYNWORD3 0x151e
#define AIU_958_SYNWORD1_MASK 0x151f
#define AIU_958_SYNWORD2_MASK 0x1520
#define AIU_958_SYNWORD3_MASK 0x1521
#define AIU_958_FFRDOUT_THD 0x1522
#define AIU_958_LENGTH_PER_PAUSE 0x1523
#define AIU_958_PAUSE_NUM 0x1524
#define AIU_958_PAUSE_PAYLOAD 0x1525
#define AIU_958_AUTO_PAUSE 0x1526
#define AIU_958_PAUSE_PD_LENGTH 0x1527
#define AIU_CODEC_DAC_LRCLK_CTRL 0x1528
#define AIU_CODEC_ADC_LRCLK_CTRL 0x1529
#define AIU_HDMI_CLK_DATA_CTRL 0x152a
#define AIU_CODEC_CLK_DATA_CTRL 0x152b
#define AIU_958_CHSTAT_R0 0x1530
#define AIU_958_CHSTAT_R1 0x1531
#define AIU_958_VALID_CTRL 0x1532
#define AIU_AUDIO_AMP_REG0 0x153c
#define AIU_AUDIO_AMP_REG1 0x153d
#define AIU_AUDIO_AMP_REG2 0x153e
#define AIU_AUDIO_AMP_REG3 0x153f
#define AIU_AIFIFO2_CTRL 0x1540
#define AIU_AIFIFO2_STATUS 0x1541
#define AIU_AIFIFO2_GBIT 0x1542
#define AIU_AIFIFO2_CLB 0x1543
#define AIU_CRC_CTRL 0x1544
#define AIU_CRC_STATUS 0x1545
#define AIU_CRC_SHIFT_REG 0x1546
#define AIU_CRC_IREG 0x1547
#define AIU_CRC_CAL_REG1 0x1548
#define AIU_CRC_CAL_REG0 0x1549
#define AIU_CRC_POLY_COEF1 0x154a
#define AIU_CRC_POLY_COEF0 0x154b
#define AIU_CRC_BIT_SIZE1 0x154c
#define AIU_CRC_BIT_SIZE0 0x154d
#define AIU_CRC_BIT_CNT1 0x154e
#define AIU_CRC_BIT_CNT0 0x154f
#define AIU_AMCLK_GATE_HI 0x1550
#define AIU_AMCLK_GATE_LO 0x1551
#define AIU_AMCLK_MSR 0x1552
#define AIU_AUDAC_CTRL0 0x1553
#define AIU_DELTA_SIGMA0 0x1555
#define AIU_DELTA_SIGMA1 0x1556
#define AIU_DELTA_SIGMA2 0x1557
#define AIU_DELTA_SIGMA3 0x1558
#define AIU_DELTA_SIGMA4 0x1559
#define AIU_DELTA_SIGMA5 0x155a
#define AIU_DELTA_SIGMA6 0x155b
#define AIU_DELTA_SIGMA7 0x155c
#define AIU_DELTA_SIGMA_LCNTS 0x155d
#define AIU_DELTA_SIGMA_RCNTS 0x155e
#define AIU_MEM_I2S_START_PTR 0x1560
#define AIU_MEM_I2S_RD_PTR 0x1561
#define AIU_MEM_I2S_END_PTR 0x1562
#define AIU_MEM_I2S_MASKS 0x1563
#define AIU_MEM_I2S_CONTROL 0x1564
#define AIU_MEM_IEC958_START_PTR 0x1565
#define AIU_MEM_IEC958_RD_PTR 0x1566
#define AIU_MEM_IEC958_END_PTR 0x1567
#define AIU_MEM_IEC958_MASKS 0x1568
#define AIU_MEM_IEC958_CONTROL 0x1569
#define AIU_MEM_AIFIFO2_START_PTR 0x156a
#define AIU_MEM_AIFIFO2_CURR_PTR 0x156b
#define AIU_MEM_AIFIFO2_END_PTR 0x156c
#define AIU_MEM_AIFIFO2_BYTES_AVAIL 0x156d
#define AIU_MEM_AIFIFO2_CONTROL 0x156e
#define AIU_MEM_AIFIFO2_MAN_WP 0x156f
#define AIU_MEM_AIFIFO2_MAN_RP 0x1570
#define AIU_MEM_AIFIFO2_LEVEL 0x1571
#define AIU_MEM_AIFIFO2_BUF_CNTL 0x1572
#define AIU_MEM_I2S_MAN_WP 0x1573
#define AIU_MEM_I2S_MAN_RP 0x1574
#define AIU_MEM_I2S_LEVEL 0x1575
#define AIU_MEM_I2S_BUF_CNTL 0x1576
#define AIU_MEM_I2S_BUF_WRAP_COUNT 0x1577
#define AIU_MEM_I2S_MEM_CTL 0x1578
#define AIU_MEM_IEC958_MEM_CTL 0x1579
#define AIU_MEM_IEC958_WRAP_COUNT 0x157a
#define AIU_MEM_IEC958_IRQ_LEVEL 0x157b
#define AIU_MEM_IEC958_MAN_WP 0x157c
#define AIU_MEM_IEC958_MAN_RP 0x157d
#define AIU_MEM_IEC958_LEVEL 0x157e
#define AIU_MEM_IEC958_BUF_CNTL 0x157f
#define AIU_AIFIFO_CTRL 0x1580
#define AIU_AIFIFO_STATUS 0x1581
#define AIU_AIFIFO_GBIT 0x1582
#define AIU_AIFIFO_CLB 0x1583
#define AIU_MEM_AIFIFO_START_PTR 0x1584
#define AIU_MEM_AIFIFO_CURR_PTR 0x1585
#define AIU_MEM_AIFIFO_END_PTR 0x1586
#define AIU_MEM_AIFIFO_BYTES_AVAIL 0x1587
#define AIU_MEM_AIFIFO_CONTROL 0x1588
#define AIU_MEM_AIFIFO_MAN_WP 0x1589
#define AIU_MEM_AIFIFO_MAN_RP 0x158a
#define AIU_MEM_AIFIFO_LEVEL 0x158b
#define AIU_MEM_AIFIFO_BUF_CNTL 0x158c
#define AIU_MEM_AIFIFO_BUF_WRAP_COUNT 0x158d
#define AIU_MEM_AIFIFO2_BUF_WRAP_COUNT 0x158e
#define AIU_MEM_AIFIFO_MEM_CTL 0x158f
#define AIFIFO_TIME_STAMP_CNTL 0x1590
#define AIFIFO_TIME_STAMP_SYNC_0 0x1591
#define AIFIFO_TIME_STAMP_SYNC_1 0x1592
#define AIFIFO_TIME_STAMP_0 0x1593
#define AIFIFO_TIME_STAMP_1 0x1594
#define AIFIFO_TIME_STAMP_2 0x1595
#define AIFIFO_TIME_STAMP_3 0x1596
#define AIFIFO_TIME_STAMP_LENGTH 0x1597
#define AIFIFO2_TIME_STAMP_CNTL 0x1598
#define AIFIFO2_TIME_STAMP_SYNC_0 0x1599
#define AIFIFO2_TIME_STAMP_SYNC_1 0x159a
#define AIFIFO2_TIME_STAMP_0 0x159b
#define AIFIFO2_TIME_STAMP_1 0x159c
#define AIFIFO2_TIME_STAMP_2 0x159d
#define AIFIFO2_TIME_STAMP_3 0x159e
#define AIFIFO2_TIME_STAMP_LENGTH 0x159f
#define IEC958_TIME_STAMP_CNTL 0x15a0
#define IEC958_TIME_STAMP_SYNC_0 0x15a1
#define IEC958_TIME_STAMP_SYNC_1 0x15a2
#define IEC958_TIME_STAMP_0 0x15a3
#define IEC958_TIME_STAMP_1 0x15a4
#define IEC958_TIME_STAMP_2 0x15a5
#define IEC958_TIME_STAMP_3 0x15a6
#define IEC958_TIME_STAMP_LENGTH 0x15a7
#define AIU_MEM_AIFIFO2_MEM_CTL 0x15a8
#define AIU_I2S_CBUS_DDR_CNTL 0x15a9
#define AIU_I2S_CBUS_DDR_WDATA 0x15aa
#define AIU_I2S_CBUS_DDR_ADDR 0x15ab
#define STB_TOP_CONFIG 0x16f0
#define TS_TOP_CONFIG 0x16f1
#define TS_FILE_CONFIG 0x16f2
#define TS_PL_PID_INDEX 0x16f3
#define TS_PL_PID_DATA 0x16f4
#define COMM_DESC_KEY0 0x16f5
#define COMM_DESC_KEY1 0x16f6
#define COMM_DESC_KEY_RW 0x16f7
#define CIPLUS_KEY0 0x16f8
#define CIPLUS_KEY1 0x16f9
#define CIPLUS_KEY2 0x16fa
#define CIPLUS_KEY3 0x16fb
#define CIPLUS_KEY_WR 0x16fc
#define CIPLUS_CONFIG 0x16fd
#define CIPLUS_ENDIAN 0x16fe
#define GE2D_GEN_CTRL0 0x18a0
#define GE2D_GEN_CTRL1 0x18a1
#define GE2D_GEN_CTRL2 0x18a2
#define GE2D_CMD_CTRL 0x18a3
#define GE2D_STATUS0 0x18a4
#define GE2D_STATUS1 0x18a5
#define GE2D_SRC1_DEF_COLOR 0x18a6
#define GE2D_SRC1_CLIPX_START_END 0x18a7
#define GE2D_SRC1_CLIPY_START_END 0x18a8
#define GE2D_SRC1_CANVAS 0x18a9
#define GE2D_SRC1_X_START_END 0x18aa
#define GE2D_SRC1_Y_START_END 0x18ab
#define GE2D_SRC1_LUT_ADDR 0x18ac
#define GE2D_SRC1_LUT_DAT 0x18ad
#define GE2D_SRC1_FMT_CTRL 0x18ae
#define GE2D_SRC2_DEF_COLOR 0x18af
#define GE2D_SRC2_CLIPX_START_END 0x18b0
#define GE2D_SRC2_CLIPY_START_END 0x18b1
#define GE2D_SRC2_X_START_END 0x18b2
#define GE2D_SRC2_Y_START_END 0x18b3
#define GE2D_DST_CLIPX_START_END 0x18b4
#define GE2D_DST_CLIPY_START_END 0x18b5
#define GE2D_DST_X_START_END 0x18b6
#define GE2D_DST_Y_START_END 0x18b7
#define GE2D_SRC2_DST_CANVAS 0x18b8
#define GE2D_VSC_START_PHASE_STEP 0x18b9
#define GE2D_VSC_PHASE_SLOPE 0x18ba
#define GE2D_VSC_INI_CTRL 0x18bb
#define GE2D_HSC_START_PHASE_STEP 0x18bc
#define GE2D_HSC_PHASE_SLOPE 0x18bd
#define GE2D_HSC_INI_CTRL 0x18be
#define GE2D_HSC_ADV_CTRL 0x18bf
#define GE2D_SC_MISC_CTRL 0x18c0
#define GE2D_VSC_NRND_POINT 0x18c1
#define GE2D_VSC_NRND_PHASE 0x18c2
#define GE2D_HSC_NRND_POINT 0x18c3
#define GE2D_HSC_NRND_PHASE 0x18c4
#define GE2D_MATRIX_PRE_OFFSET 0x18c5
#define GE2D_MATRIX_COEF00_01 0x18c6
#define GE2D_MATRIX_COEF02_10 0x18c7
#define GE2D_MATRIX_COEF11_12 0x18c8
#define GE2D_MATRIX_COEF20_21 0x18c9
#define GE2D_MATRIX_COEF22_CTRL 0x18ca
#define GE2D_MATRIX_OFFSET 0x18cb
#define GE2D_ALU_OP_CTRL 0x18cc
#define GE2D_ALU_CONST_COLOR 0x18cd
#define GE2D_SRC1_KEY 0x18ce
#define GE2D_SRC1_KEY_MASK 0x18cf
#define GE2D_SRC2_KEY 0x18d0
#define GE2D_SRC2_KEY_MASK 0x18d1
#define GE2D_DST_BITMASK 0x18d2
#define GE2D_DP_ONOFF_CTRL 0x18d3
#define GE2D_SCALE_COEF_IDX 0x18d4
#define GE2D_SCALE_COEF 0x18d5
#define GE2D_SRC_OUTSIDE_ALPHA 0x18d6
#define GE2D_ANTIFLICK_CTRL0 0x18d8
#define GE2D_ANTIFLICK_CTRL1 0x18d9
#define GE2D_ANTIFLICK_COLOR_FILT0 0x18da
#define GE2D_ANTIFLICK_COLOR_FILT1 0x18db
#define GE2D_ANTIFLICK_COLOR_FILT2 0x18dc
#define GE2D_ANTIFLICK_COLOR_FILT3 0x18dd
#define GE2D_ANTIFLICK_ALPHA_FILT0 0x18de
#define GE2D_ANTIFLICK_ALPHA_FILT1 0x18df
#define GE2D_ANTIFLICK_ALPHA_FILT2 0x18e0
#define GE2D_ANTIFLICK_ALPHA_FILT3 0x18e1
#define GE2D_SRC1_RANGE_MAP_Y_CTRL 0x18e3
#define GE2D_SRC1_RANGE_MAP_CB_CTRL 0x18e4
#define GE2D_SRC1_RANGE_MAP_CR_CTRL 0x18e5
#define GE2D_ARB_BURST_NUM 0x18e6
#define GE2D_TID_TOKEN 0x18e7
#define GE2D_GEN_CTRL3 0x18e8
#define GE2D_STATUS2 0x18e9
#define GE2D_GEN_CTRL4 0x18ea
#define AUDIO_COP_CTL2 0x1f01
#define OPERAND_M_CTL 0x1f02
#define OPERAND1_ADDR 0x1f03
#define OPERAND2_ADDR 0x1f04
#define RESULT_M_CTL 0x1f05
#define RESULT1_ADDR 0x1f06
#define RESULT2_ADDR 0x1f07
#define ADD_SHFT_CTL 0x1f08
#define OPERAND_ONE_H 0x1f09
#define OPERAND_ONE_L 0x1f0a
#define OPERAND_TWO_H 0x1f0b
#define OPERAND_TWO_L 0x1f0c
#define RESULT_H 0x1f0d
#define RESULT_M 0x1f0e
#define RESULT_L 0x1f0f
#define WMEM_R_PTR 0x1f10
#define WMEM_W_PTR 0x1f11
#define AUDIO_LAYER 0x1f20
#define AC3_DECODING 0x1f21
#define AC3_DYNAMIC 0x1f22
#define AC3_MELODY 0x1f23
#define AC3_VOCAL 0x1f24
#define ASSIST_AMR_SCRATCH0 0x1f4f
#define ASSIST_AMR_SCRATCH1 0x1f50
#define ASSIST_AMR_SCRATCH2 0x1f51
#define ASSIST_AMR_SCRATCH3 0x1f52
#define ASSIST_HW_REV 0x1f53
#define ASSIST_POR_CONFIG 0x1f55
#define ASSIST_SPARE16_REG1 0x1f56
#define ASSIST_SPARE16_REG2 0x1f57
#define ASSIST_SPARE8_REG1 0x1f58
#define ASSIST_SPARE8_REG2 0x1f59
#define ASSIST_SPARE8_REG3 0x1f5a
#define AC3_CTRL_REG1 0x1f5b
#define AC3_CTRL_REG2 0x1f5c
#define AC3_CTRL_REG3 0x1f5d
#define AC3_CTRL_REG4 0x1f5e
#define ASSIST_GEN_CNTL 0x1f68
#define EE_ASSIST_MBOX0_IRQ_REG 0x1f70
#define EE_ASSIST_MBOX0_CLR_REG 0x1f71
#define EE_ASSIST_MBOX0_MASK 0x1f72
#define EE_ASSIST_MBOX0_FIQ_SEL 0x1f73
#define EE_ASSIST_MBOX1_IRQ_REG 0x1f74
#define EE_ASSIST_MBOX1_CLR_REG 0x1f75
#define EE_ASSIST_MBOX1_MASK 0x1f76
#define EE_ASSIST_MBOX1_FIQ_SEL 0x1f77
#define EE_ASSIST_MBOX2_IRQ_REG 0x1f78
#define EE_ASSIST_MBOX2_CLR_REG 0x1f79
#define EE_ASSIST_MBOX2_MASK 0x1f7a
#define EE_ASSIST_MBOX2_FIQ_SEL 0x1f7b
#define EE_ASSIST_MBOX3_IRQ_REG 0x1f7c
#define EE_ASSIST_MBOX3_CLR_REG 0x1f7d
#define EE_ASSIST_MBOX3_MASK 0x1f7e
#define EE_ASSIST_MBOX3_FIQ_SEL 0x1f7f
#define PREG_CTLREG0_ADDR 0x2000
#define PREG_PAD_GPIO6_EN_N 0x2008
#define PREG_PAD_GPIO6_O 0x2009
#define PREG_PAD_GPIO6_I 0x200a
#define PREG_JTAG_GPIO_ADDR 0x200b
#define PREG_PAD_GPIO0_EN_N 0x200c
#define PREG_PAD_GPIO0_O 0x200d
#define PREG_PAD_GPIO0_I 0x200e
#define PREG_PAD_GPIO1_EN_N 0x200f
#define PREG_PAD_GPIO1_O 0x2010
#define PREG_PAD_GPIO1_I 0x2011
#define PREG_PAD_GPIO2_EN_N 0x2012
#define PREG_PAD_GPIO2_O 0x2013
#define PREG_PAD_GPIO2_I 0x2014
#define PREG_PAD_GPIO3_EN_N 0x2015
#define PREG_PAD_GPIO3_O 0x2016
#define PREG_PAD_GPIO3_I 0x2017
#define PREG_PAD_GPIO4_EN_N 0x2018
#define PREG_PAD_GPIO4_O 0x2019
#define PREG_PAD_GPIO4_I 0x201a
#define PREG_PAD_GPIO5_EN_N 0x201b
#define PREG_PAD_GPIO5_O 0x201c
#define PREG_PAD_GPIO5_I 0x201d
#define A9_STATUS1 0x201f
#define A9_CFG0 0x2020
#define A9_CFG1 0x2021
#define A9_CFG2 0x2022
#define A9_PERIPH_BASE 0x2023
#define A9_L2_REG_BASE 0x2024
#define A9_L2_STATUS 0x2025
#define A9_POR_CFG 0x2026
#define A9_STATUS2 0x2027
#define AXI_REG_EN 0x2028
#define A9_CFG3 0x2029
#define A9_CFG4 0x202a
#define A9_STATUS3 0x202b
#define PERIPHS_PIN_MUX_0 0x202c
#define PERIPHS_PIN_MUX_1 0x202d
#define PERIPHS_PIN_MUX_2 0x202e
#define PERIPHS_PIN_MUX_3 0x202f
#define PERIPHS_PIN_MUX_4 0x2030
#define PERIPHS_PIN_MUX_5 0x2031
#define PERIPHS_PIN_MUX_6 0x2032
#define PERIPHS_PIN_MUX_7 0x2033
#define PERIPHS_PIN_MUX_8 0x2034
#define PERIPHS_PIN_MUX_9 0x2035
#define PERIPHS_PIN_MUX_10 0x2036
#define PERIPHS_PIN_MUX_11 0x2037
#define PERIPHS_PIN_MUX_12 0x2038
#define PAD_PULL_UP_REG6 0x2039
#define PAD_PULL_UP_REG0 0x203a
#define PAD_PULL_UP_REG1 0x203b
#define PAD_PULL_UP_REG2 0x203c
#define PAD_PULL_UP_REG3 0x203d
#define PAD_PULL_UP_REG4 0x203e
#define PAD_PULL_UP_REG5 0x203f
#define RAND64_ADDR0 0x2040
#define RAND64_ADDR1 0x2041
#define PREG_ETHERNET_ADDR0 0x2042
#define PREG_AM_ANALOG_ADDR 0x2043
#define PREG_MALI_BYTE_CNTL 0x2044
#define PREG_WIFI_CNTL 0x2045
#define PAD_PULL_UP_EN_REG0 0x2048
#define PAD_PULL_UP_EN_REG1 0x2049
#define PAD_PULL_UP_EN_REG2 0x204a
#define PAD_PULL_UP_EN_REG3 0x204b
#define PAD_PULL_UP_EN_REG4 0x204c
#define PAD_PULL_UP_EN_REG5 0x204d
#define PAD_PULL_UP_EN_REG6 0x204e
#define PREG_ETH_REG0 0x2050
#define PREG_ETH_REG1 0x2051
#define PROD_TEST_REG1 0x2067
#define PROD_TEST_REG0 0x2068
#define METAL_REVISION 0x206a
#define ADC_TOP_MISC 0x206b
#define DPLL_TOP_MISC 0x206c
#define ANALOG_TOP_MISC 0x206d
#define AM_ANALOG_TOP_REG0 0x206e
#define AM_ANALOG_TOP_REG1 0x206f
#define PREG_STICKY_REG0 0x207c
#define PREG_STICKY_REG1 0x207d
#define PREG_WRITE_ONCE_REG 0x207e
#define AM_RING_OSC_REG0 0x207f
#define SMARTCARD_REG0 0x2110
#define SMARTCARD_REG1 0x2111
#define SMARTCARD_REG2 0x2112
#define SMARTCARD_STATUS 0x2113
#define SMARTCARD_INTR 0x2114
#define SMARTCARD_REG5 0x2115
#define SMARTCARD_REG6 0x2116
#define SMARTCARD_FIFO 0x2117
#define SMARTCARD_REG8 0x2118
#define IR_DEC_LDR_ACTIVE 0x2120
#define IR_DEC_LDR_IDLE 0x2121
#define IR_DEC_LDR_REPEAT 0x2122
#define IR_DEC_BIT_0 0x2123
#define IR_DEC_REG0 0x2124
#define IR_DEC_FRAME 0x2125
#define IR_DEC_STATUS 0x2126
#define IR_DEC_REG1 0x2127
#define DEMOD_ADC_SAMPLING 0x212d
#define UART0_WFIFO 0x2130
#define UART0_RFIFO 0x2131
#define UART0_CONTROL 0x2132
#define UART0_STATUS 0x2133
#define UART0_MISC 0x2134
#define UART0_REG5 0x2135
#define UART1_WFIFO 0x2137
#define UART1_RFIFO 0x2138
#define UART1_CONTROL 0x2139
#define UART1_STATUS 0x213a
#define UART1_MISC 0x213b
#define UART1_REG5 0x213c
#define I2C_M_0_CONTROL_REG 0x2140
#define I2C_M_0_SLAVE_ADDR 0x2141
#define I2C_M_0_TOKEN_LIST0 0x2142
#define I2C_M_0_TOKEN_LIST1 0x2143
#define I2C_M_0_WDATA_REG0 0x2144
#define I2C_M_0_WDATA_REG1 0x2145
#define I2C_M_0_RDATA_REG0 0x2146
#define I2C_M_0_RDATA_REG1 0x2147
#define I2C_S_CONTROL_REG 0x2150
#define I2C_S_SEND_REG 0x2151
#define I2C_S_RECV_REG 0x2152
#define I2C_S_CNTL1_REG 0x2153
#define PWM_PWM_A 0x2154
#define PWM_PWM_B 0x2155
#define PWM_MISC_REG_AB 0x2156
#define PWM_DELTA_SIGMA_AB 0x2157
#define ATAPI_IDEREG0 0x2160
#define ATAPI_IDEREG1 0x2161
#define ATAPI_IDEREG2 0x2162
#define ATAPI_CYCTIME 0x2163
#define ATAPI_IDETIME 0x2164
#define ATAPI_PIO_TIMING 0x2165
#define ATAPI_TABLE_ADD_REG 0x2166
#define ATAPI_IDEREG3 0x2167
#define ATAPI_UDMA_REG0 0x2168
#define ATAPI_UDMA_REG1 0x2169
#define TRANS_PWMA_REG0 0x2170
#define TRANS_PWMA_REG1 0x2171
#define TRANS_PWMA_MUX0 0x2172
#define TRANS_PWMA_MUX1 0x2173
#define TRANS_PWMA_MUX2 0x2174
#define TRANS_PWMA_MUX3 0x2175
#define TRANS_PWMA_MUX4 0x2176
#define TRANS_PWMA_MUX5 0x2177
#define TRANS_PWMB_REG0 0x2178
#define TRANS_PWMB_REG1 0x2179
#define TRANS_PWMB_MUX0 0x217a
#define TRANS_PWMB_MUX1 0x217b
#define TRANS_PWMB_MUX2 0x217c
#define TRANS_PWMB_MUX3 0x217d
#define TRANS_PWMB_MUX4 0x217e
#define TRANS_PWMB_MUX5 0x217f
#define NAND_START 0x2180
#define NAND_ADR_CMD 0x218a
#define NAND_ADR_STS 0x218b
#define NAND_END 0x218f
#define PWM_PWM_C 0x2194
#define PWM_PWM_D 0x2195
#define PWM_MISC_REG_CD 0x2196
#define PWM_DELTA_SIGMA_CD 0x2197
#define ISP_LED_CTRL 0x2198
#define ISP_LED_TIMING1 0x2199
#define ISP_LED_TIMING2 0x219a
#define ISP_LED_TIMING3 0x219b
#define ISP_LED_TIMING4 0x219c
#define ISP_LED_TIMING5 0x219d
#define ISP_LED_TIMING6 0x219e
#define SAR_ADC_REG0 0x21a0
#define SAR_ADC_CHAN_LIST 0x21a1
#define SAR_ADC_AVG_CNTL 0x21a2
#define SAR_ADC_REG3 0x21a3
#define SAR_ADC_DELAY 0x21a4
#define SAR_ADC_LAST_RD 0x21a5
#define SAR_ADC_FIFO_RD 0x21a6
#define SAR_ADC_AUX_SW 0x21a7
#define SAR_ADC_CHAN_10_SW 0x21a8
#define SAR_ADC_DETECT_IDLE_SW 0x21a9
#define SAR_ADC_DELTA_10 0x21aa
#define PWM_PWM_E 0x21b0
#define PWM_PWM_F 0x21b1
#define PWM_MISC_REG_EF 0x21b2
#define PWM_DELTA_SIGMA_EF 0x21b3
#define UART2_WFIFO 0x21c0
#define UART2_RFIFO 0x21c1
#define UART2_CONTROL 0x21c2
#define UART2_STATUS 0x21c3
#define UART2_MISC 0x21c4
#define UART2_REG5 0x21c5
#define UART3_WFIFO 0x21c8
#define UART3_RFIFO 0x21c9
#define UART3_CONTROL 0x21ca
#define UART3_STATUS 0x21cb
#define UART3_MISC 0x21cc
#define UART3_REG5 0x21cd
#define RTC_ADDR0 0x21d0
#define RTC_ADDR1 0x21d1
#define RTC_ADDR2 0x21d2
#define RTC_ADDR3 0x21d3
#define RTC_ADDR4 0x21d4
#define MSR_CLK_DUTY 0x21d6
#define MSR_CLK_REG0 0x21d7
#define MSR_CLK_REG1 0x21d8
#define MSR_CLK_REG2 0x21d9
#define LED_PWM_REG0 0x21da
#define MSR_CLK_REG3 0x21da
#define LED_PWM_REG1 0x21db
#define MSR_CLK_REG4 0x21db
#define LED_PWM_REG2 0x21dc
#define LED_PWM_REG3 0x21dd
#define LED_PWM_REG4 0x21de
#define MSR_CLK_REG5 0x21de
#define LED_PWM_REG5 0x21df
#define LED_PWM_REG6 0x21e0
#define VGHL_PWM_REG0 0x21e1
#define VGHL_PWM_REG1 0x21e2
#define VGHL_PWM_REG2 0x21e3
#define VGHL_PWM_REG3 0x21e4
#define VGHL_PWM_REG4 0x21e5
#define VGHL_PWM_REG5 0x21e6
#define VGHL_PWM_REG6 0x21e7
#define I2C_M_1_CONTROL_REG 0x21f0
#define I2C_M_1_SLAVE_ADDR 0x21f1
#define I2C_M_1_TOKEN_LIST0 0x21f2
#define I2C_M_1_TOKEN_LIST1 0x21f3
#define I2C_M_1_WDATA_REG0 0x21f4
#define I2C_M_1_WDATA_REG1 0x21f5
#define I2C_M_1_RDATA_REG0 0x21f6
#define I2C_M_1_RDATA_REG1 0x21f7
#define I2C_M_2_CONTROL_REG 0x21f8
#define I2C_M_2_SLAVE_ADDR 0x21f9
#define I2C_M_2_TOKEN_LIST0 0x21fa
#define I2C_M_2_TOKEN_LIST1 0x21fb
#define I2C_M_2_WDATA_REG0 0x21fc
#define I2C_M_2_WDATA_REG1 0x21fd
#define I2C_M_2_RDATA_REG0 0x21fe
#define I2C_M_2_RDATA_REG1 0x21ff
#define USB_ADDR0 0x2200
#define USB_ADDR1 0x2201
#define USB_ADDR2 0x2202
#define USB_ADDR3 0x2203
#define USB_ADDR4 0x2204
#define USB_ADDR5 0x2205
#define USB_ADDR6 0x2206
#define USB_ADDR7 0x2207
#define USB_ADDR8 0x2208
#define USB_ADDR9 0x2209
#define USB_ADDR10 0x220a
#define USB_ADDR11 0x220b
#define USB_ADDR12 0x220c
#define USB_ADDR13 0x220d
#define USB_ADDR14 0x220e
#define USB_ADDR15 0x220f
#define USB_ADDR16 0x2210
#define USB_ADDR17 0x2211
#define USB_ADDR18 0x2212
#define USB_ADDR19 0x2213
#define USB_ADDR20 0x2214
#define USB_ADDR21 0x2215
#define USB_ADDR22 0x2216
#define USB_ADDR23 0x2217
#define USB_ADDR24 0x2218
#define USB_ADDR25 0x2219
#define USB_ADDR26 0x221a
#define USB_ADDR27 0x221b
#define USB_ADDR28 0x221c
#define USB_ADDR29 0x221d
#define USB_ADDR30 0x221e
#define USB_ADDR31 0x221f
#define SANA_STREAM_CONTROL 0x2220
#define SANA_STREAM_START_ADDR 0x2221
#define SANA_STREAM_END_ADDR 0x2222
#define SANA_STREAM_WR_PTR 0x2223
#define SANA_STREAM_RD_PTR 0x2224
#define SANA_STREAM_LEVEL 0x2225
#define SANA_STREAM_FIFO_CTL 0x2226
#define SANA_SHIFT_CONTROL 0x2227
#define SANA_SHIFT_STARTCODE 0x2228
#define SANA_SHIFT_EMULATECODE 0x2229
#define SANA_SHIFT_STATUS 0x222a
#define SANA_SHIFTED_DATA 0x222b
#define SANA_SHIFT_BYTE_COUNT 0x222c
#define SANA_SHIFT_COMMAND 0x222d
#define SANA_ELEMENT_RESULT 0x222e
#define ATOM_LOCK 0x222f
#define NDMA_CNTL_REG0 0x2270
#define NDMA_TABLE_ADD_REG 0x2272
#define NDMA_TDES_KEY_LO 0x2273
#define NDMA_TDES_KEY_HI 0x2274
#define NDMA_TDES_CONTROL 0x2275
#define NDMA_RIJNDAEL_CONTROL 0x2276
#define NDMA_RIJNDAEL_RK_FIFO 0x2277
#define NDMA_CRC_OUT 0x2278
#define NDMA_THREAD_REG 0x2279
#define NDMA_THREAD_TABLE_START0 0x2280
#define NDMA_THREAD_TABLE_CURR0 0x2281
#define NDMA_THREAD_TABLE_END0 0x2282
#define NDMA_THREAD_TABLE_START1 0x2283
#define NDMA_THREAD_TABLE_CURR1 0x2284
#define NDMA_THREAD_TABLE_END1 0x2285
#define NDMA_THREAD_TABLE_START2 0x2286
#define NDMA_THREAD_TABLE_CURR2 0x2287
#define NDMA_THREAD_TABLE_END2 0x2288
#define NDMA_THREAD_TABLE_START3 0x2289
#define NDMA_THREAD_TABLE_CURR3 0x228a
#define NDMA_THREAD_TABLE_END3 0x228b
#define NDMA_CNTL_REG1 0x228c
#define NDMA_AES_KEY_0 0x2290
#define NDMA_AES_KEY_1 0x2291
#define NDMA_AES_KEY_2 0x2292
#define NDMA_AES_KEY_3 0x2293
#define NDMA_AES_KEY_4 0x2294
#define NDMA_AES_KEY_5 0x2295
#define NDMA_AES_KEY_6 0x2296
#define NDMA_AES_KEY_7 0x2297
#define NDMA_AES_IV_0 0x2298
#define NDMA_AES_IV_1 0x2299
#define NDMA_AES_IV_2 0x229a
#define NDMA_AES_IV_3 0x229b
#define NDMA_AES_REG0 0x229c
#define STREAM_EVENT_INFO 0x2300
#define STREAM_OUTPUT_CONFIG 0x2301
#define C_D_BUS_CONTROL 0x2302
#define C_DATA 0x2303
#define STREAM_BUS_CONFIG 0x2304
#define STREAM_DATA_IN_CONFIG 0x2305
#define STREAM_WAIT_IRQ_CONFIG 0x2306
#define STREAM_EVENT_CTL 0x2307
#define CMD_ARGUMENT 0x2308
#define CMD_SEND 0x2309
#define SDIO_CONFIG 0x230a
#define SDIO_STATUS_IRQ 0x230b
#define SDIO_IRQ_CONFIG 0x230c
#define SDIO_MULT_CONFIG 0x230d
#define SDIO_M_ADDR 0x230e
#define SDIO_EXTENSION 0x230f
#define ASYNC_FIFO_REG0 0x2310
#define ASYNC_FIFO_REG1 0x2311
#define ASYNC_FIFO_REG2 0x2312
#define ASYNC_FIFO_REG3 0x2313
#define ASYNC_FIFO2_REG0 0x2314
#define ASYNC_FIFO2_REG1 0x2315
#define ASYNC_FIFO2_REG2 0x2316
#define ASYNC_FIFO2_REG3 0x2317
#define SDIO_AHB_CBUS_CTRL 0x2318
#define SDIO_AHB_CBUS_M_DATA 0x2319
#define SPI_FLASH_CMD 0x2320
#define SPI_FLASH_ADDR 0x2321
#define SPI_FLASH_CTRL 0x2322
#define SPI_FLASH_CTRL1 0x2323
#define SPI_FLASH_STATUS 0x2324
#define SPI_FLASH_CTRL2 0x2325
#define SPI_FLASH_CLOCK 0x2326
#define SPI_FLASH_USER 0x2327
#define SPI_FLASH_USER1 0x2328
#define SPI_FLASH_USER2 0x2329
#define SPI_FLASH_USER3 0x232a
#define SPI_FLASH_USER4 0x232b
#define SPI_FLASH_SLAVE 0x232c
#define SPI_FLASH_SLAVE1 0x232d
#define SPI_FLASH_SLAVE2 0x232e
#define SPI_FLASH_SLAVE3 0x232f
#define SPI_FLASH_C0 0x2330
#define SPI_FLASH_C1 0x2331
#define SPI_FLASH_C2 0x2332
#define SPI_FLASH_C3 0x2333
#define SPI_FLASH_C4 0x2334
#define SPI_FLASH_C5 0x2335
#define SPI_FLASH_C6 0x2336
#define SPI_FLASH_C7 0x2337
#define SPI_FLASH_B8 0x2338
#define SPI_FLASH_B9 0x2339
#define SPI_FLASH_B10 0x233a
#define SPI_FLASH_B11 0x233b
#define SPI_FLASH_B12 0x233c
#define SPI_FLASH_B13 0x233d
#define SPI_FLASH_B14 0x233e
#define SPI_FLASH_B15 0x233f
#define I2C_M_3_CONTROL_REG 0x2348
#define I2C_M_3_SLAVE_ADDR 0x2349
#define I2C_M_3_TOKEN_LIST0 0x234a
#define I2C_M_3_TOKEN_LIST1 0x234b
#define I2C_M_3_WDATA_REG0 0x234c
#define I2C_M_3_WDATA_REG1 0x234d
#define I2C_M_3_RDATA_REG0 0x234e
#define I2C_M_3_RDATA_REG1 0x234f
#define SPICC_RXDATA 0x2360
#define SPICC_TXDATA 0x2361
#define SPICC_CONREG 0x2362
#define SPICC_INTREG 0x2363
#define SPICC_DMAREG 0x2364
#define SPICC_STATREG 0x2365
#define SPICC_PERIODREG 0x2366
#define SPICC_TESTREG 0x2367
#define SPICC_DRADDR 0x2368
#define SPICC_DWADDR 0x2369
#define SD_REG0_ARGU 0x2380
#define SD_REG1_SEND 0x2381
#define SD_REG2_CNTL 0x2382
#define SD_REG3_STAT 0x2383
#define SD_REG4_CLKC 0x2384
#define SD_REG5_ADDR 0x2385
#define SD_REG6_PDMA 0x2386
#define SD_REG7_MISC 0x2387
#define SD_REG8_DATA 0x2388
#define SD_REG9_ICTL 0x2389
#define SD_REGA_ISTA 0x238a
#define SD_REGB_SRST 0x238b
#define SD_REGC_ESTA 0x238c
#define SD_REGD_ENHC 0x238d
#define SD_REGE_CLK2 0x238e
#define IQ_OM_WIDTH 0x2510
#define ISA_DEBUG_REG0 0x2600
#define ISA_DEBUG_REG1 0x2601
#define ISA_DEBUG_REG2 0x2602
#define ISA_DEBUG_REG3 0x2603
#define ISA_PLL_CLK_SIM0 0x2608
#define ISA_CNTL_REG0 0x2609
#define AO_CPU_IRQ_IN0_INTR_STAT 0x2610
#define AO_CPU_IRQ_IN0_INTR_STAT_CLR 0x2611
#define AO_CPU_IRQ_IN0_INTR_MASK 0x2612
#define AO_CPU_IRQ_IN0_INTR_FIRQ_SEL 0x2613
#define GPIO_INTR_EDGE_POL 0x2620
#define GPIO_INTR_GPIO_SEL0 0x2621
#define GPIO_INTR_GPIO_SEL1 0x2622
#define GPIO_INTR_FILTER_SEL0 0x2623
#define MEDIA_CPU_INTR_STAT 0x2628
#define MEDIA_CPU_INTR_STAT_CLR 0x2629
#define MEDIA_CPU_INTR_MASK 0x262a
#define MEDIA_CPU_INTR_FIRQ_SEL 0x262b
#define ISA_BIST_REG0 0x2630
#define ISA_BIST_REG1 0x2631
#define WATCHDOG_TC 0x2640
#define WATCHDOG_RESET 0x2641
#define AHB_ARBITER_REG 0x2642
#define AHB_ARBDEC_REG 0x2643
#define AHB_ARBITER2_REG 0x264a
#define DEVICE_MMCP_CNTL 0x264b
#define AUDIO_MMCP_CNTL 0x264c
#define ISA_TIMER_MUX 0x2650
#define ISA_TIMERA 0x2651
#define ISA_TIMERB 0x2652
#define ISA_TIMERC 0x2653
#define ISA_TIMERD 0x2654
#define ISA_TIMERE 0x2655
#define FBUF_ADDR 0x2656
#define SDRAM_CTL0 0x2657
#define SDRAM_CTL2 0x2658
#define SDRAM_CTL4 0x265a
#define SDRAM_CTL5 0x265b
#define SDRAM_CTL6 0x265c
#define SDRAM_CTL7 0x265d
#define SDRAM_CTL8 0x265e
#define AHB_MP4_MC_CTL 0x265f
#define MEDIA_CPU_PCR 0x2660
#define MEDIA_CPU_CTL 0x2661
#define ISA_TIMER_MUX1 0x2664
#define ISA_TIMERF 0x2665
#define ISA_TIMERG 0x2666
#define ISA_TIMERH 0x2667
#define ISA_TIMERI 0x2668
#define ABUF_WR_CTL0 0x2670
#define ABUF_WR_CTL1 0x2671
#define ABUF_WR_CTL2 0x2672
#define ABUF_WR_CTL3 0x2673
#define ABUF_RD_CTL0 0x2674
#define ABUF_RD_CTL1 0x2675
#define ABUF_RD_CTL2 0x2676
#define ABUF_RD_CTL3 0x2677
#define ABUF_ARB_CTL0 0x2678
#define ABUF_FIFO_CTL0 0x2679
#define AHB_BRIDGE_CNTL_WR 0x2680
#define AHB_BRIDGE_REMAP0 0x2681
#define AHB_BRIDGE_REMAP1 0x2682
#define AHB_BRIDGE_REMAP2 0x2683
#define AHB_BRIDGE_REMAP3 0x2684
#define AHB_BRIDGE_CNTL_REG1 0x2685
#define AHB_BRIDGE_CNTL_REG2 0x2686
#define AUDIN_SPDIF_MODE 0x2800
#define AUDIN_SPDIF_FS_CLK_RLTN 0x2801
#define AUDIN_SPDIF_CHNL_STS_A 0x2802
#define AUDIN_SPDIF_CHNL_STS_B 0x2803
#define AUDIN_SPDIF_MISC 0x2804
#define AUDIN_SPDIF_NPCM_PCPD 0x2805
#define AUDIN_SPDIF_END 0x280f
#define AUDIN_I2SIN_CTRL 0x2810
#define AUDIN_SOURCE_SEL 0x2811
#define AUDIN_DECODE_FORMAT 0x2812
#define AUDIN_DECODE_CONTROL_STATUS 0x2813
#define AUDIN_DECODE_CHANNEL_STATUS_A_0 0x2814
#define AUDIN_DECODE_CHANNEL_STATUS_A_1 0x2815
#define AUDIN_DECODE_CHANNEL_STATUS_A_2 0x2816
#define AUDIN_DECODE_CHANNEL_STATUS_A_3 0x2817
#define AUDIN_DECODE_CHANNEL_STATUS_A_4 0x2818
#define AUDIN_DECODE_CHANNEL_STATUS_A_5 0x2819
#define AUDIN_FIFO0_START 0x2820
#define AUDIN_FIFO0_END 0x2821
#define AUDIN_FIFO0_PTR 0x2822
#define AUDIN_FIFO0_INTR 0x2823
#define AUDIN_FIFO0_RDPTR 0x2824
#define AUDIN_FIFO0_CTRL 0x2825
#define AUDIN_FIFO0_CTRL1 0x2826
#define AUDIN_FIFO0_LVL0 0x2827
#define AUDIN_FIFO0_LVL1 0x2828
#define AUDIN_FIFO0_LVL2 0x2829
#define AUDIN_FIFO0_REQID 0x2830
#define AUDIN_FIFO0_WRAP 0x2831
#define AUDIN_FIFO1_START 0x2833
#define AUDIN_FIFO1_END 0x2834
#define AUDIN_FIFO1_PTR 0x2835
#define AUDIN_FIFO1_INTR 0x2836
#define AUDIN_FIFO1_RDPTR 0x2837
#define AUDIN_FIFO1_CTRL 0x2838
#define AUDIN_FIFO1_CTRL1 0x2839
#define AUDIN_FIFO1_LVL0 0x2840
#define AUDIN_FIFO1_LVL1 0x2841
#define AUDIN_FIFO1_LVL2 0x2842
#define AUDIN_FIFO1_REQID 0x2843
#define AUDIN_FIFO1_WRAP 0x2844
#define AUDIN_FIFO2_START 0x2845
#define AUDIN_FIFO2_END 0x2846
#define AUDIN_FIFO2_PTR 0x2847
#define AUDIN_FIFO2_INTR 0x2848
#define AUDIN_FIFO2_RDPTR 0x2849
#define AUDIN_FIFO2_CTRL 0x284a
#define AUDIN_FIFO2_CTRL1 0x284b
#define AUDIN_FIFO2_LVL0 0x284c
#define AUDIN_FIFO2_LVL1 0x284d
#define AUDIN_FIFO2_LVL2 0x284e
#define AUDIN_FIFO2_REQID 0x284f
#define AUDIN_FIFO2_WRAP 0x2850
#define AUDIN_INT_CTRL 0x2851
#define AUDIN_FIFO_INT 0x2852
#define PCMIN_CTRL0 0x2860
#define PCMIN_CTRL1 0x2861
#define PCMOUT_CTRL0 0x2870
#define PCMOUT_CTRL1 0x2871
#define PCMOUT_CTRL2 0x2872
#define PCMOUT_CTRL3 0x2873
#define AUDOUT_CTRL 0x2880
#define AUDOUT_CTRL1 0x2881
#define AUDOUT_BUF0_STA 0x2882
#define AUDOUT_BUF0_EDA 0x2883
#define AUDOUT_BUF0_WPTR 0x2884
#define AUDOUT_BUF1_STA 0x2885
#define AUDOUT_BUF1_EDA 0x2886
#define AUDOUT_BUF1_WPTR 0x2887
#define AUDOUT_FIFO_RPTR 0x2888
#define AUDOUT_INTR_PTR 0x2889
#define AUDOUT_FIFO_STS 0x288a
#define AUDIN_HDMI_MEAS_CTRL 0x28a0
#define AUDIN_HDMI_MEAS_CYCLES_M1 0x28a1
#define AUDIN_HDMI_MEAS_INTR_MASKN 0x28a2
#define AUDIN_HDMI_MEAS_INTR_STAT 0x28a3
#define AUDIN_HDMI_REF_CYCLES_STAT_0 0x28a4
#define AUDIN_HDMI_REF_CYCLES_STAT_1 0x28a5
#define AUDIN_HDMIRX_AFIFO_STAT 0x28a6
#define AUDIN_FIFO0_PIO_STS 0x28b0
#define AUDIN_FIFO0_PIO_RDL 0x28b1
#define AUDIN_FIFO0_PIO_RDH 0x28b2
#define AUDIN_FIFO1_PIO_STS 0x28b3
#define AUDIN_FIFO1_PIO_RDL 0x28b4
#define AUDIN_FIFO1_PIO_RDH 0x28b5
#define AUDIN_FIFO2_PIO_STS 0x28b6
#define AUDIN_FIFO2_PIO_RDL 0x28b7
#define AUDIN_FIFO2_PIO_RDH 0x28b8
#define AUDOUT_FIFO_PIO_STS 0x28b9
#define AUDOUT_FIFO_PIO_WRL 0x28ba
#define AUDOUT_FIFO_PIO_WRH 0x28bb
#define AUDIN_ADDR_END 0x28bf
#define PARSER_CONTROL 0x2960
#define PARSER_FETCH_ADDR 0x2961
#define PARSER_FETCH_CMD 0x2962
#define PARSER_FETCH_STOP_ADDR 0x2963
#define PARSER_FETCH_LEVEL 0x2964
#define PARSER_CONFIG 0x2965
#define PFIFO_WR_PTR 0x2966
#define PFIFO_RD_PTR 0x2967
#define PFIFO_DATA 0x2968
#define PARSER_SEARCH_PATTERN 0x2969
#define PARSER_SEARCH_MASK 0x296a
#define PARSER_INT_ENABLE 0x296b
#define PARSER_INT_STATUS 0x296c
#define PARSER_SCR_CTL 0x296d
#define PARSER_SCR 0x296e
#define PARSER_PARAMETER 0x296f
#define PARSER_INSERT_DATA 0x2970
#define VAS_STREAM_ID 0x2971
#define VIDEO_DTS 0x2972
#define VIDEO_PTS 0x2973
#define VIDEO_PTS_DTS_WR_PTR 0x2974
#define AUDIO_PTS 0x2975
#define AUDIO_PTS_WR_PTR 0x2976
#define PARSER_ES_CONTROL 0x2977
#define PFIFO_MONITOR 0x2978
#define PARSER_VIDEO_START_PTR 0x2980
#define PARSER_VIDEO_END_PTR 0x2981
#define PARSER_VIDEO_WP 0x2982
#define PARSER_VIDEO_RP 0x2983
#define PARSER_VIDEO_HOLE 0x2984
#define PARSER_AUDIO_START_PTR 0x2985
#define PARSER_AUDIO_END_PTR 0x2986
#define PARSER_AUDIO_WP 0x2987
#define PARSER_AUDIO_RP 0x2988
#define PARSER_AUDIO_HOLE 0x2989
#define PARSER_SUB_START_PTR 0x298a
#define PARSER_SUB_END_PTR 0x298b
#define PARSER_SUB_WP 0x298c
#define PARSER_SUB_RP 0x298d
#define PARSER_SUB_HOLE 0x298e
#define PARSER_FETCH_INFO 0x298f
#define PARSER_STATUS 0x2990
#define PARSER_AV_WRAP_COUNT 0x2991
#define WRRSP_PARSER 0x2992
#define PARSER_VIDEO2_START_PTR 0x2993
#define PARSER_VIDEO2_END_PTR 0x2994
#define PARSER_VIDEO2_WP 0x2995
#define PARSER_VIDEO2_RP 0x2996
#define PARSER_VIDEO2_HOLE 0x2997
#define PARSER_AV2_WRAP_COUNT 0x2998
#define DBG_ADDR_START 0x2ff0
#define DBG_CTRL 0x2ff1
#define DBG_LED 0x2ff2
#define DBG_SWITCH 0x2ff3
#define DBG_VERSION 0x2ff4
#define DBG_ADDR_END 0x2fff