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  1. ****************
  2. The decoded data
  3. ****************
  4. ==================
  5. Signature
  6. Stepping 11
  7. Model 15
  8. Family 6
  9. Type 0
  10.  
  11. ======================================
  12. Processor: Intel(R) Core(R) 2 Duo
  13.  
  14. =============================
  15. Process 65 nm
  16.  
  17. ================== BrandName ====================
  18. Intel(R) Core(TM)2 Duo CPU T7800 @ 2.60GHz
  19. =================================================
  20.  
  21. =============================
  22. Maximal frequency 2600 MHz
  23.  
  24. ==============================================================
  25. IPP would recommend using cpu_v8(u8) code for this processor
  26.  
  27. =====================================
  28. TLB and Cache Parameters (Function 2)
  29. =====================================
  30. ---------------------
  31. Instruction TLB 0
  32. ---------------------
  33. PageSize Kb 4
  34. way 4
  35. entries 128
  36.  
  37. ---------------------
  38. Instruction TLB 1
  39. ---------------------
  40. PageSize Kb 4096
  41. way 4
  42. entries 4
  43.  
  44. ---------------------
  45. L0 Data TLB 0
  46. ---------------------
  47. PageSize Kb 4
  48. way 4
  49. entries 32
  50.  
  51. ---------------------
  52. L0 Data TLB 1
  53. ---------------------
  54. PageSize Kb 4096
  55. way 4
  56. entries 4
  57.  
  58. ---------------------
  59. Data TLB1 0
  60. ---------------------
  61. PageSize Kb 4096
  62. way 4
  63. entries 32
  64.  
  65. ---------------------
  66. Data TLB1 1
  67. ---------------------
  68. PageSize Kb 4
  69. way 4
  70. entries 256
  71.  
  72. ---------------------
  73. L1 Instruction Cache
  74. ---------------------
  75. size Kb 32
  76. way 8
  77. lineSize Bytes 64
  78.  
  79. ---------------------
  80. L1 Data Cache
  81. ---------------------
  82. size Kb 32
  83. way 8
  84. lineSize Bytes 64
  85.  
  86. ---------------------
  87. L2 Data Cache
  88. ---------------------
  89. size Kb 4096
  90. way 16
  91. lineSize Bytes 64
  92.  
  93. =============================
  94. Bytes Prefetching 64
  95.  
  96. ================================
  97. Cache Parameters (Function 4)
  98. ================================
  99.  
  100. CacheType 1 - Data Cache
  101. CacheLevel 1
  102. SelfInit 1
  103. FullyAssociat 0
  104. NumbeThreadsSharing 1
  105. NumberSets 64
  106. PrefetchStride 128
  107. SysCoherencyLineSize 64
  108. LinePartitions 1
  109. WaysAssociat 8
  110. CacheSizeKb 32
  111.  
  112. CacheType 2 - Instruction Cache
  113. CacheLevel 1
  114. SelfInit 1
  115. FullyAssociat 0
  116. NumbeThreadsSharing 1
  117. NumberSets 64
  118. PrefetchStride 128
  119. SysCoherencyLineSize 64
  120. LinePartitions 1
  121. WaysAssociat 8
  122. CacheSizeKb 32
  123.  
  124. CacheType 3 - Unified Cache
  125. CacheLevel 2
  126. SelfInit 1
  127. FullyAssociat 0
  128. NumbeThreadsSharing 2
  129. NumberSets 4096
  130. PrefetchStride 128
  131. SysCoherencyLineSize 64
  132. LinePartitions 1
  133. WaysAssociat 16
  134. CacheSizeKb 4096
  135.  
  136.  
  137. ================
  138. Feature Flags
  139. ================
  140. Cores 2 - Number of cores per physical package
  141. CMP / HTT 1 - Multi-Cores and/or Multi-Threading
  142. LogPerPhysCPU 2 - Number of logical processors per physical processor package
  143.  
  144. FPU 1 - The Intel387 floating-point instruction set is supported
  145. RDTSC 1 - The RDTSC instruction is supported
  146. MSR 1 - Model Specific Registers ( RDMSR, WRMSR )
  147. FXSR 1 - The FXSAVE and the FXRSTOR instructions are supported
  148. CMPXCHG8 1 - The CMPXCHG8 instruction is supported
  149. CMPXCHG16B 1 - The CMPXCHG16B instruction is supported
  150. CLFLUSH 1 - The CLFLUSH instruction is supported
  151. CMOV 1 - CMOVcc, (if FPU - FCMOVCC,FCOMI) are supported
  152. SEP 1 - Fast System Call ( SYSENTER / SYSEXIT )
  153. SYSCALL 0 - SYSCALL / SYSRET
  154. LAHF 1 - LAHF / SAHF
  155. MONITOR 1 - MONITOR / MWAIT instruction are supported
  156. MOVBE 0 - MOVBE instruction. For the first time in Bonnell.
  157. POPCNT 0 - CPU supports the POPCNT instruction.
  158.  
  159. MMX 1 - Intel(R) Architecture MMX(TM) technology is supported
  160. SSE 1 - Streaming SIMD Extensions is supported. Pentium(R) III)
  161. SSE2 1 - Streaming SIMD Extensions 2 is supported.(Pentium(R) 4)
  162. SSE3 1 - Streaming SIMD Extensions 3 is supported.(Prescott)
  163. SSSE3 1 - Supplemental Streaming SIMD Extensions 3 is supported.(Merom)
  164. SSE41 0 - Streaming SIMD Extensions 4 (SSE4.1) is supported.(Penryn)
  165. SSE42 0 - Streaming SIMD Extensions 4 (SSE4.2) is supported.(Nehalem)
  166. STTNI 0 - STTNI Instructions, Nehalem first instance.
  167. EM64T 1 - Intel(R) Extended Memory 64 Technology is supported
  168.  
  169. VME 1 - Virtual Mode Extension is supported
  170. DE 1 - Debugging Extension
  171. PSE 1 - Page Size Extension. CPU supports 4-Mbyte pages
  172. PAE 1 - Physical addresses greater than 32 bits are supported
  173. MCE 1 - Machine Check Exception (18)
  174. APIC 1 - On-chip APIC Hardware Supported
  175. MTRR 1 - Memory Type Range Registers
  176. PGE 1 - Page Global Enable
  177. MCA 1 - Machine Check Architecture
  178. PAT 1 - Page Attribute Table
  179. PSE-36 1 - 36-bit Page Size Extension
  180. DS 1 - Debug Store
  181. ACPI 1 - Advanced Configuration and Power Interface
  182. SS 1 - Self-Snoop
  183. TM 1 - Thermal Monitor
  184. IA64 0 - Intel(R) Itanium(R) operating in IA32 emulation mode
  185. PBE 1 - Pending Break Enable
  186. DSCPL 1 - CPL Qualified Debug Store
  187. VMX 1 - Virtual Machine Extensions
  188. EST 1 - Enhanced Intel SpeedStep(R) Technology is supported
  189. TM2 1 - Thermal Monitor 2
  190. CID 0 - Context ID (L1 data cache mode)
  191. xTPR 1 - Send Task Priority Messages
  192. DCA 0 - Direct Cache Access
  193.  
  194. =========================================
  195. MONITOR / MWAIT Parameters (Function 5)
  196. =========================================
  197. Smallest monitor line size in bytes 64
  198. Largest monitor line size in bytes 64
  199. MONITOR / MWAIT Extensions supported 1
  200. Support for treating interrupts as break-events for MWAIT 1
  201. Number of C4 sub-states supported using MONITOR / MWAIT 2
  202. Number of C3 sub-states supported using MONITOR / MWAIT 2
  203. Number of C2 sub-states supported using MONITOR / MWAIT 2
  204. Number of C1 sub-states supported using MONITOR / MWAIT 2
  205. Number of C0 sub-states supported using MONITOR / MWAIT 0
  206.  
  207. =====================================================================
  208. Digital Thermal Sensor and Power Management Parameters (Function 6)
  209. =====================================================================
  210. Digital Thermal Sensor Capability 1
  211. Number of Interrupt Thresholds 2
  212. Hardware Coordination Feedback Capability 1
  213.  
  214. =================================================
  215. Extended L2 Cache Features (Function 80000006h)
  216. =================================================
  217. L2 Cache size described in 1024-byte units 4096
  218. L2 Cache Associativity 16-Way
  219. L2 Cache Line Size in bytes 64
  220.  
  221. =========================================================
  222. Virtual and Physical address Sizes (Function 80000008h)
  223. =========================================================
  224. Virtual Address Size: Number of address bits 48
  225. Physical Address Size: Number of address bits 36
  226.  
  227. =======================
  228. Warning bits[2:0] = 0
  229. =======================
  230. Warning bit[0] = 1: It is required more than one call CPUID.2
  231. (Changes in instruction CPUID)
  232. Warning bit[1] = 1: Unknown code (cache or TLB) in CPUID.2
  233. (It is required to add tables in the file ippgetcpuinfo.c)
  234. Warning bit[2] = 1: Code ECX CPUID.4 is more than 31
  235. (Changes in instruction CPUID)
  236.  
  237. ***************
  238. The binary data
  239. ***************
  240. =====================================
  241. Largest Standard Function number: 10
  242. =====================================
  243. Function 0
  244. eax = 0000000A
  245. ebx = 756E6547
  246. ecx = 6C65746E
  247. edx = 49656E69
  248. Function 1
  249. eax = 000006FB
  250. ebx = 00020800
  251. ecx = 0000E3BD
  252. edx = BFEBFBFF
  253. Function 2
  254. eax = 05B0B101
  255. ebx = 005657F0
  256. ecx = 00000000
  257. edx = 2CB43049
  258. Function 3
  259. eax = 00000000
  260. ebx = 00000000
  261. ecx = 00000000
  262. edx = 00000000
  263. Function 4
  264. eax = 04000121
  265. ebx = 01C0003F
  266. ecx = 0000003F
  267. edx = 00000001
  268. Function 5
  269. eax = 00000040
  270. ebx = 00000040
  271. ecx = 00000003
  272. edx = 00022220
  273. Function 6
  274. eax = 00000001
  275. ebx = 00000002
  276. ecx = 00000001
  277. edx = 00000000
  278. Function 7
  279. eax = 00000000
  280. ebx = 00000000
  281. ecx = 00000000
  282. edx = 00000000
  283. Function 8
  284. eax = 00000400
  285. ebx = 00000000
  286. ecx = 00000000
  287. edx = 00000000
  288. Function 9
  289. eax = 00000000
  290. ebx = 00000000
  291. ecx = 00000000
  292. edx = 00000000
  293. Function 10
  294. eax = 07280202
  295. ebx = 00000000
  296. ecx = 00000000
  297. edx = 00000503
  298. =======================================
  299. Largest number for Function 4 in ECX: 2
  300. =======================================
  301. Function 4 0
  302. eax = 04000121
  303. ebx = 01C0003F
  304. ecx = 0000003F
  305. edx = 00000001
  306. Function 4 1
  307. eax = 04000122
  308. ebx = 01C0003F
  309. ecx = 0000003F
  310. edx = 00000001
  311. Function 4 2
  312. eax = 04004143
  313. ebx = 03C0003F
  314. ecx = 00000FFF
  315. edx = 00000001
  316. =====================================
  317. Largest Extended Function number: 8
  318. =====================================
  319. Function 80000000h
  320. eax = 80000008
  321. ebx = 00000000
  322. ecx = 00000000
  323. edx = 00000000
  324. Function 80000001h
  325. eax = 00000000
  326. ebx = 00000000
  327. ecx = 00000001
  328. edx = 20100000
  329. Function 80000002h
  330. eax = 65746E49
  331. ebx = 2952286C
  332. ecx = 726F4320
  333. edx = 4D542865
  334. Function 80000003h
  335. eax = 44203229
  336. ebx = 43206F75
  337. ecx = 20205550
  338. edx = 54202020
  339. Function 80000004h
  340. eax = 30303837
  341. ebx = 20402020
  342. ecx = 30362E32
  343. edx = 007A4847
  344. Function 80000005h
  345. eax = 00000000
  346. ebx = 00000000
  347. ecx = 00000000
  348. edx = 00000000
  349. Function 80000006h
  350. eax = 00000000
  351. ebx = 00000000
  352. ecx = 10008040
  353. edx = 00000000
  354. Function 80000007h
  355. eax = 00000000
  356. ebx = 00000000
  357. ecx = 00000000
  358. edx = 00000000
  359. Function 80000008h
  360. eax = 00003024
  361. ebx = 00000000
  362. ecx = 00000000
  363. edx = 00000000
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