From 6e58bc0c9d5fa1d5fc914b385b94c95193fb0561 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <festevam@gmail.com>
Date: Mon, 29 Aug 2016 16:37:06 -0300
Subject: [PATCH 1/2] mx6: ddr: Allow changing REFSEL and REFR fields

Allow the SPL DDR initialization code to override the default
configurations for the REFSEL and REFR fields of the MDREF register.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
 arch/arm/cpu/armv7/mx6/ddr.c            | 15 ++++++++++++---
 arch/arm/include/asm/arch-mx6/mx6-ddr.h |  2 ++
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index f151eec..ebc7903 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -1183,7 +1183,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	volatile struct mmdc_p_regs *mmdc0;
 	volatile struct mmdc_p_regs *mmdc1;
 	u32 val;
-	u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
+	u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd, refsel, refr;
 	u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
 	u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
 	u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
@@ -1472,8 +1472,17 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 		MMDC1(mpzqhwctrl, val);

 	/* Step 12: Configure and activate periodic refresh */
-	mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
-		       (7 << 11);  /* REFR: Refresh Rate - 8 refreshes */
+	if (!sysinfo->refsel)
+		refsel = 1; /* REF_SEL: Periodic refresh cycle: 32kHz */
+	else
+		refsel = sysinfo->refsel;
+
+	if (!sysinfo->refr)
+		refr = 7; /* REFR: Refresh Rate - 8 refreshes */
+	else
+		refr = sysinfo->refr;
+
+	mmdc0->mdref = (refsel << 14) | (refr << 11);

 	/* Step 13: Deassert config request - init complete */
 	mmdc0->mdscr = 0x00000000;
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 12c30d2..819ec19 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -408,6 +408,8 @@ struct mx6_ddr_sysinfo {
 	u8 sde_to_rst;	/* Time from SDE enable until DDR reset# is high */
 	u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
 	u8 ddr_type;	/* DDR type: DDR3(0) or LPDDR2(1) */
+	u8 refsel;
+	u8 refr;
 };

 /*
--
1.9.1