sram1x4

library ieee;
use ieee.std_logic_1164.all;

entity Sram1b4 is
	port(data : in std_logic_vector(3 downto 0);
			we, cs, oe, chipSel: in std_logic;
			qout : out std_logic_vector(3 downto 0));
end Sram1b4;

architecture arch of Sram1b4 is

	component SRAMCell
		port( inp, sel, WEna: in std_logic;
				qout: out std_logic);
	end component;

	component tlb
		port(a_in, b_in : in std_logic;
				a_out : out std_logic);
	end component;

	signal wecs, csoe: std_logic;
	signal beforeout : std_logic_vector(3 downto 0);

	begin

	wecs <= we and cs;
	csoe <= cs and oe;

	Sram1: SraMCell
		port map (data(3), chipSel, wecs, beforeout(3));
	Sram2: SraMCell
		port map (data(2), chipSel, wecs, beforeout(2));
	Sram3: SraMCell
		port map (data(1), chipSel, wecs, beforeout(1));
	Sram4: SramCell
		port map (data(0), chipSel, wecs, beforeout(0));
	dataout3: tlb
		port map (beforeout(3), csoe, qout(3));
	dataout2: tlb
		port map (beforeout(2), csoe, qout(2));
	dataout1: tlb
		port map (beforeout(1), csoe, qout(1));
	dataout0: tlb
		port map (beforeout(0), csoe, qout(0));
end arch;