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  1. $ sudo pcm.x 1
  2. Password:
  3.  
  4. Intel(r) Performance Counter Monitor V2.8 (2014-12-18 12:52:39 +0100 ID=ba39a89)
  5.  
  6. Copyright (c) 2009-2014 Intel Corporation
  7.  
  8. cpuctl(4) not loaded.
  9. Delay: 1
  10. Access to Intel(r) Performance Counter Monitor has denied (no MSR or PCI CFG space access).
  11. $ sudo kldload cpuctl
  12. $ sudo pcm.x 1
  13.  
  14. Intel(r) Performance Counter Monitor V2.8 (2014-12-18 12:52:39 +0100 ID=ba39a89)
  15.  
  16. Copyright (c) 2009-2014 Intel Corporation
  17.  
  18. Number of physical cores: 4
  19. Number of logical cores: 8
  20. Number of online logical cores: 8
  21. Threads (logical cores) per physical core: 2
  22. Num sockets: 1
  23. Physical cores per socket: 4
  24. Core PMU (perfmon) version: 3
  25. Number of core PMU generic (programmable) counters: 4
  26. Width of generic (programmable) counters: 48 bits
  27. Number of core PMU fixed counters: 3
  28. Width of fixed counters: 48 bits
  29. Nominal core frequency: 2200000000 Hz
  30. Package thermal spec power: 35 Watt; Package minimum power: 24 Watt; Package maximum power: 0 Watt;
  31. Delay: 1
  32.  
  33. Detected Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz "Intel(r) microarchitecture codename Ivy Bridge"
  34.  
  35. EXEC : instructions per nominal CPU cycle
  36. IPC : instructions per CPU cycle
  37. FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost)
  38. AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost)
  39. L3MISS: L3 cache misses
  40. L2MISS: L2 cache misses (including other core's L2 cache *hits*)
  41. L3HIT : L3 cache hit ratio (0.00-1.00)
  42. L2HIT : L2 cache hit ratio (0.00-1.00)
  43. L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency
  44. L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00)
  45. READ : bytes read from memory controller (in GBytes)
  46. WRITE : bytes written to memory controller (in GBytes)
  47. IO : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests
  48. TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature
  49.  
  50.  
  51. Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE | IO | TEMP |
  52.  
  53. 0 0 0.00 0.39 0.00 1.04 599 2186 0.73 0.38 0.04 0.03 N/A N/A N/A 64
  54. 1 0 0.00 0.76 0.00 0.72 70 308 0.77 0.45 0.10 0.09 N/A N/A N/A 64
  55. 2 0 0.00 1.20 0.00 0.56 223 3988 0.94 0.70 0.03 0.16 N/A N/A N/A 62
  56. 3 0 0.00 0.68 0.00 0.68 73 335 0.78 0.48 0.09 0.10 N/A N/A N/A 62
  57. 4 0 0.00 0.91 0.00 0.56 2030 4611 0.56 0.70 0.37 0.15 N/A N/A N/A 62
  58. 5 0 0.00 1.75 0.00 0.63 48 191 0.75 0.74 0.03 0.03 N/A N/A N/A 62
  59. 6 0 0.00 0.70 0.00 0.82 32 69 0.54 0.66 0.06 0.02 N/A N/A N/A 58
  60. 7 0 0.00 0.64 0.00 0.76 90 187 0.52 0.56 0.11 0.03 N/A N/A N/A 58
  61. -----------------------------------------------------------------------------------------------------------------------------
  62. SKT 0 0.00 0.73 0.00 0.75 3165 11 K 0.73 0.66 0.10 0.08 0.24 0.01 0.24 58
  63. -----------------------------------------------------------------------------------------------------------------------------
  64. TOTAL * 0.00 0.73 0.00 0.75 3165 11 K 0.73 0.66 0.10 0.08 0.24 0.01 0.24 N/A
  65.  
  66. Instructions retired: 4268 K ; Active cycles: 5857 K ; Time (TSC): 2334 Mticks ; C0 (active,non-halted) core residency: 0.04 %
  67.  
  68. C1 core residency: 99.96 %; C3 core residency: 0.00 %; C6 core residency: 0.00 %; C7 core residency: 0.00 %;
  69. C2 package residency: 0.00 %; C3 package residency: 0.00 %; C6 package residency: 0.00 %; C7 package residency: 0.00 %;
  70.  
  71. PHYSICAL CORE IPC : 1.46 => corresponds to 36.44 % utilization for cores in active state
  72. Instructions per nominal CPU cycle: 0.00 => corresponds to 0.01 % core utilization over time interval
  73. ----------------------------------------------------------------------------------------------
  74.  
  75. ----------------------------------------------------------------------------------------------
  76. SKT 0 package consumed 6.70 Joules
  77. ----------------------------------------------------------------------------------------------
  78. TOTAL: 6.70 Joules
  79.  
  80. EXEC : instructions per nominal CPU cycle
  81. IPC : instructions per CPU cycle
  82. FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost)
  83. AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost)
  84. L3MISS: L3 cache misses
  85. L2MISS: L2 cache misses (including other core's L2 cache *hits*)
  86. L3HIT : L3 cache hit ratio (0.00-1.00)
  87. L2HIT : L2 cache hit ratio (0.00-1.00)
  88. L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency
  89. L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00)
  90. READ : bytes read from memory controller (in GBytes)
  91. WRITE : bytes written to memory controller (in GBytes)
  92. IO : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests
  93. TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature
  94.  
  95.  
  96. Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE | IO | TEMP |
  97.  
  98. 0 0 0.00 0.40 0.00 1.02 163 1511 0.89 0.52 0.01 0.02 N/A N/A N/A 63
  99. 1 0 0.00 0.71 0.00 1.03 2702 4727 0.43 0.40 0.51 0.09 N/A N/A N/A 63
  100. 2 0 0.00 1.19 0.00 0.56 46 3816 0.99 0.71 0.01 0.16 N/A N/A N/A 61
  101. 3 0 0.00 0.56 0.00 0.80 15 192 0.92 0.59 0.02 0.06 N/A N/A N/A 61
  102. 4 0 0.00 0.90 0.00 0.57 1930 4495 0.57 0.71 0.33 0.15 N/A N/A N/A 63
  103. 5 0 0.00 2.02 0.00 0.60 13 131 0.90 0.86 0.01 0.02 N/A N/A N/A 63
  104. 6 0 0.00 0.50 0.00 0.79 9 40 0.78 0.69 0.01 0.01 N/A N/A N/A 58
  105. 7 0 0.00 1.12 0.00 1.14 155 304 0.49 0.71 0.04 0.01 N/A N/A N/A 58
  106. -----------------------------------------------------------------------------------------------------------------------------
  107. SKT 0 0.00 0.78 0.00 0.80 5033 15 K 0.67 0.64 0.12 0.07 0.24 0.01 0.24 58
  108. -----------------------------------------------------------------------------------------------------------------------------
  109. TOTAL * 0.00 0.78 0.00 0.80 5033 15 K 0.67 0.64 0.12 0.07 0.24 0.01 0.24 N/A
  110.  
  111. Instructions retired: 5878 K ; Active cycles: 7503 K ; Time (TSC): 2329 Mticks ; C0 (active,non-halted) core residency: 0.05 %
  112.  
  113. C1 core residency: 99.95 %; C3 core residency: 0.00 %; C6 core residency: 0.00 %; C7 core residency: 0.00 %;
  114. C2 package residency: 0.00 %; C3 package residency: 0.00 %; C6 package residency: 0.00 %; C7 package residency: 0.00 %;
  115.  
  116. PHYSICAL CORE IPC : 1.57 => corresponds to 39.17 % utilization for cores in active state
  117. Instructions per nominal CPU cycle: 0.00 => corresponds to 0.02 % core utilization over time interval
  118. ----------------------------------------------------------------------------------------------
  119.  
  120. ----------------------------------------------------------------------------------------------
  121. SKT 0 package consumed 6.69 Joules
  122. ----------------------------------------------------------------------------------------------
  123. TOTAL: 6.69 Joules
  124.  
  125. EXEC : instructions per nominal CPU cycle
  126. IPC : instructions per CPU cycle
  127. FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost)
  128. AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost)
  129. L3MISS: L3 cache misses
  130. L2MISS: L2 cache misses (including other core's L2 cache *hits*)
  131. L3HIT : L3 cache hit ratio (0.00-1.00)
  132. L2HIT : L2 cache hit ratio (0.00-1.00)
  133. L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency
  134. L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00)
  135. READ : bytes read from memory controller (in GBytes)
  136. WRITE : bytes written to memory controller (in GBytes)
  137. IO : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests
  138. TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature
  139.  
  140.  
  141. Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE | IO | TEMP |
  142.  
  143. 0 0 0.00 0.40 0.00 1.03 201 1757 0.89 0.47 0.01 0.02 N/A N/A N/A 64
  144. 1 0 0.00 0.87 0.00 0.94 346 2084 0.83 0.54 0.07 0.09 N/A N/A N/A 64
  145. 2 0 0.00 1.14 0.00 0.58 152 4662 0.97 0.68 0.02 0.17 N/A N/A N/A 61
  146. 3 0 0.00 0.60 0.00 0.72 50 251 0.80 0.51 0.06 0.07 N/A N/A N/A 61
  147. 4 0 0.00 0.86 0.00 0.57 2116 4962 0.57 0.70 0.32 0.14 N/A N/A N/A 63
  148. 5 0 0.00 0.91 0.00 0.61 70 411 0.83 0.70 0.04 0.06 N/A N/A N/A 63
  149. 6 0 0.00 0.54 0.00 0.68 138 289 0.52 0.41 0.11 0.04 N/A N/A N/A 57
  150. 7 0 0.00 1.16 0.00 1.03 41 233 0.82 0.73 0.01 0.02 N/A N/A N/A 57
  151. -----------------------------------------------------------------------------------------------------------------------------
  152. SKT 0 0.00 0.75 0.00 0.78 3114 14 K 0.79 0.65 0.07 0.08 0.24 0.01 0.24 57
  153. -----------------------------------------------------------------------------------------------------------------------------
  154. TOTAL * 0.00 0.75 0.00 0.78 3114 14 K 0.79 0.65 0.07 0.08 0.24 0.01 0.24 N/A
  155.  
  156. Instructions retired: 5933 K ; Active cycles: 7861 K ; Time (TSC): 2332 Mticks ; C0 (active,non-halted) core residency: 0.05 %
  157.  
  158. C1 core residency: 99.95 %; C3 core residency: 0.00 %; C6 core residency: 0.00 %; C7 core residency: 0.00 %;
  159. C2 package residency: 0.00 %; C3 package residency: 0.00 %; C6 package residency: 0.00 %; C7 package residency: 0.00 %;
  160.  
  161. PHYSICAL CORE IPC : 1.51 => corresponds to 37.74 % utilization for cores in active state
  162. Instructions per nominal CPU cycle: 0.00 => corresponds to 0.02 % core utilization over time interval
  163. ----------------------------------------------------------------------------------------------
  164.  
  165. ----------------------------------------------------------------------------------------------
  166. SKT 0 package consumed 6.70 Joules
  167. ----------------------------------------------------------------------------------------------
  168. TOTAL: 6.70 Joules
  169.  
  170. EXEC : instructions per nominal CPU cycle
  171. IPC : instructions per CPU cycle
  172. FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost)
  173. AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost)
  174. L3MISS: L3 cache misses
  175. L2MISS: L2 cache misses (including other core's L2 cache *hits*)
  176. L3HIT : L3 cache hit ratio (0.00-1.00)
  177. L2HIT : L2 cache hit ratio (0.00-1.00)
  178. L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency
  179. L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00)
  180. READ : bytes read from memory controller (in GBytes)
  181. WRITE : bytes written to memory controller (in GBytes)
  182. IO : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests
  183. TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature
  184.  
  185.  
  186. Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE | IO | TEMP |
  187.  
  188. 0 0 0.00 0.41 0.00 1.02 147 1277 0.88 0.51 0.01 0.02 N/A N/A N/A 65
  189. 1 0 0.00 1.14 0.00 0.93 227 1206 0.81 0.67 0.05 0.05 N/A N/A N/A 65
  190. 2 0 0.00 1.22 0.00 0.57 65 3791 0.98 0.71 0.01 0.16 N/A N/A N/A 61
  191. 3 0 0.00 0.90 0.00 0.78 13 89 0.85 0.62 0.02 0.04 N/A N/A N/A 61
  192. 4 0 0.00 0.92 0.00 0.56 2007 4635 0.57 0.70 0.36 0.16 N/A N/A N/A 64
  193. 5 0 0.00 0.70 0.00 0.68 8 105 0.92 0.87 0.01 0.03 N/A N/A N/A 64
  194. 6 0 0.00 0.70 0.00 0.74 10 104 0.90 0.66 0.01 0.03 N/A N/A N/A 58
  195. 7 0 0.00 1.26 0.00 1.19 9 94 0.90 0.84 0.00 0.01 N/A N/A N/A 58
  196. -----------------------------------------------------------------------------------------------------------------------------
  197. SKT 0 0.00 0.80 0.00 0.80 2486 11 K 0.78 0.69 0.06 0.07 0.24 0.01 0.24 58
  198. -----------------------------------------------------------------------------------------------------------------------------
  199. TOTAL * 0.00 0.80 0.00 0.80 2486 11 K 0.78 0.69 0.06 0.07 0.24 0.01 0.24 N/A
  200.  
  201. Instructions retired: 5585 K ; Active cycles: 6945 K ; Time (TSC): 2333 Mticks ; C0 (active,non-halted) core residency: 0.05 %
  202.  
  203. C1 core residency: 99.95 %; C3 core residency: 0.00 %; C6 core residency: 0.00 %; C7 core residency: 0.00 %;
  204. C2 package residency: 0.00 %; C3 package residency: 0.00 %; C6 package residency: 0.00 %; C7 package residency: 0.00 %;
  205.  
  206. PHYSICAL CORE IPC : 1.61 => corresponds to 40.20 % utilization for cores in active state
  207. Instructions per nominal CPU cycle: 0.00 => corresponds to 0.01 % core utilization over time interval
  208. ----------------------------------------------------------------------------------------------
  209.  
  210. ----------------------------------------------------------------------------------------------
  211. SKT 0 package consumed 6.69 Joules
  212. ----------------------------------------------------------------------------------------------
  213. TOTAL: 6.69 Joules
  214. ^CDEBUG: caught signal to interrupt (Interrupt).
  215. Cleaning up
  216. Zeroed PMU registers
  217. Freeing up all RMIDs
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