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  1. [ember@FreeBSD ~]$ pcm.x 1
  2.  
  3. Intel(r) Performance Counter Monitor V2.8 (2014-12-18 12:52:39 +0100 ID=ba39a89)
  4.  
  5. Copyright (c) 2009-2014 Intel Corporation
  6.  
  7. Number of physical cores: 1
  8. Number of logical cores: 8
  9. Number of online logical cores: 8
  10. Threads (logical cores) per physical core: 8
  11. Num sockets: 1
  12. Physical cores per socket: 1
  13. Core PMU (perfmon) version: 3
  14. Number of core PMU generic (programmable) counters: 4
  15. Width of generic (programmable) counters: 48 bits
  16. Number of core PMU fixed counters: 3
  17. Width of fixed counters: 48 bits
  18. Can not access CPUs Model Specific Registers (MSRs).
  19. Ensure cpuctl module is loaded and that you have read and write
  20. permissions for /dev/cpuctl* devices (the 'chown' command can help).
  21. Delay: 1
  22. Access to Intel(r) Performance Counter Monitor has denied (no MSR or PCI CFG space access).
  23. [ember@FreeBSD ~]$ sudo pcm.x 1
  24.  
  25. Intel(r) Performance Counter Monitor V2.8 (2014-12-18 12:52:39 +0100 ID=ba39a89)
  26.  
  27. Copyright (c) 2009-2014 Intel Corporation
  28.  
  29. Number of physical cores: 4
  30. Number of logical cores: 8
  31. Number of online logical cores: 8
  32. Threads (logical cores) per physical core: 2
  33. Num sockets: 1
  34. Physical cores per socket: 4
  35. Core PMU (perfmon) version: 3
  36. Number of core PMU generic (programmable) counters: 4
  37. Width of generic (programmable) counters: 48 bits
  38. Number of core PMU fixed counters: 3
  39. Width of fixed counters: 48 bits
  40. Nominal core frequency: 2200000000 Hz
  41. Package thermal spec power: 35 Watt; Package minimum power: 24 Watt; Package maximum power: 0 Watt;
  42. Delay: 1
  43.  
  44. Detected Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz "Intel(r) microarchitecture codename Ivy Bridge"
  45.  
  46. EXEC : instructions per nominal CPU cycle
  47. IPC : instructions per CPU cycle
  48. FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost)
  49. AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost)
  50. L3MISS: L3 cache misses
  51. L2MISS: L2 cache misses (including other core's L2 cache *hits*)
  52. L3HIT : L3 cache hit ratio (0.00-1.00)
  53. L2HIT : L2 cache hit ratio (0.00-1.00)
  54. L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency
  55. L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00)
  56. READ : bytes read from memory controller (in GBytes)
  57. WRITE : bytes written to memory controller (in GBytes)
  58. IO : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests
  59. TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature
  60.  
  61.  
  62. Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE | IO | TEMP |
  63.  
  64. 0 0 0.00 0.23 0.00 0.55 20 K 22 K 0.06 0.01 1.03 0.01 N/A N/A N/A 75
  65. 1 0 0.00 0.24 0.00 0.55 8552 9044 0.05 0.01 1.42 0.02 N/A N/A N/A 75
  66. 2 0 0.00 0.47 0.00 0.55 7583 8003 0.05 0.00 1.08 0.02 N/A N/A N/A 75
  67. 3 0 0.00 0.23 0.00 0.55 6082 6370 0.05 0.00 1.42 0.02 N/A N/A N/A 75
  68. 4 0 0.00 0.21 0.00 0.55 51 K 57 K 0.10 0.00 1.40 0.03 N/A N/A N/A 75
  69. 5 0 0.00 0.19 0.00 0.55 6777 6950 0.02 0.00 1.60 0.01 N/A N/A N/A 75
  70. 6 0 0.00 0.35 0.00 0.55 24 K 26 K 0.09 0.00 1.00 0.02 N/A N/A N/A 75
  71. 7 0 0.00 0.29 0.00 0.55 5230 5365 0.03 0.03 1.39 0.01 N/A N/A N/A 75
  72. -----------------------------------------------------------------------------------------------------------------------------
  73. SKT 0 0.00 0.27 0.00 0.55 130 K 141 K 0.08 0.00 1.23 0.02 0.37 0.00 0.36 74
  74. -----------------------------------------------------------------------------------------------------------------------------
  75. TOTAL * 0.00 0.27 0.00 0.55 130 K 141 K 0.08 0.00 1.23 0.02 0.37 0.00 0.36 N/A
  76.  
  77. Instructions retired: 5108 K ; Active cycles: 19 M ; Time (TSC): 2335 Mticks ; C0 (active,non-halted) core residency: 0.19 %
  78.  
  79. C1 core residency: 0.24 %; C3 core residency: 0.23 %; C6 core residency: 0.00 %; C7 core residency: 99.34 %;
  80. C2 package residency: 1.26 %; C3 package residency: 0.22 %; C6 package residency: 0.62 %; C7 package residency: 96.38 %;
  81.  
  82. PHYSICAL CORE IPC : 0.53 => corresponds to 13.29 % utilization for cores in active state
  83. Instructions per nominal CPU cycle: 0.00 => corresponds to 0.01 % core utilization over time interval
  84. ----------------------------------------------------------------------------------------------
  85.  
  86. ----------------------------------------------------------------------------------------------
  87. SKT 0 package consumed 3.34 Joules
  88. ----------------------------------------------------------------------------------------------
  89. TOTAL: 3.34 Joules
  90.  
  91. EXEC : instructions per nominal CPU cycle
  92. IPC : instructions per CPU cycle
  93. FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost)
  94. AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost)
  95. L3MISS: L3 cache misses
  96. L2MISS: L2 cache misses (including other core's L2 cache *hits*)
  97. L3HIT : L3 cache hit ratio (0.00-1.00)
  98. L2HIT : L2 cache hit ratio (0.00-1.00)
  99. L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency
  100. L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00)
  101. READ : bytes read from memory controller (in GBytes)
  102. WRITE : bytes written to memory controller (in GBytes)
  103. IO : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests
  104. TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature
  105.  
  106.  
  107. Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE | IO | TEMP |
  108.  
  109. 0 0 0.00 0.25 0.00 0.55 27 K 29 K 0.07 0.03 1.11 0.02 N/A N/A N/A 76
  110. 1 0 0.00 0.24 0.00 0.55 4943 6357 0.22 0.01 0.92 0.06 N/A N/A N/A 76
  111. 2 0 0.00 0.39 0.00 0.55 7678 7980 0.04 0.00 1.19 0.01 N/A N/A N/A 76
  112. 3 0 0.00 0.23 0.00 0.55 8499 10 K 0.16 0.00 1.00 0.05 N/A N/A N/A 76
  113. 4 0 0.00 0.21 0.00 0.55 48 K 55 K 0.12 0.00 1.28 0.03 N/A N/A N/A 76
  114. 5 0 0.00 0.31 0.00 0.55 12 K 13 K 0.05 0.07 1.21 0.01 N/A N/A N/A 76
  115. 6 0 0.00 0.35 0.00 0.55 23 K 25 K 0.08 0.00 1.04 0.02 N/A N/A N/A 76
  116. 7 0 0.00 0.51 0.00 0.55 9961 10 K 0.05 0.03 0.88 0.01 N/A N/A N/A 76
  117. -----------------------------------------------------------------------------------------------------------------------------
  118. SKT 0 0.00 0.29 0.00 0.55 142 K 157 K 0.10 0.01 1.12 0.03 0.37 0.00 0.36 75
  119. -----------------------------------------------------------------------------------------------------------------------------
  120. TOTAL * 0.00 0.29 0.00 0.55 142 K 157 K 0.10 0.01 1.12 0.03 0.37 0.00 0.36 N/A
  121.  
  122. Instructions retired: 6595 K ; Active cycles: 22 M ; Time (TSC): 2335 Mticks ; C0 (active,non-halted) core residency: 0.22 %
  123.  
  124. C1 core residency: 0.30 %; C3 core residency: 0.36 %; C6 core residency: 0.00 %; C7 core residency: 99.12 %;
  125. C2 package residency: 1.34 %; C3 package residency: 0.35 %; C6 package residency: 0.54 %; C7 package residency: 96.06 %;
  126.  
  127. PHYSICAL CORE IPC : 0.58 => corresponds to 14.45 % utilization for cores in active state
  128. Instructions per nominal CPU cycle: 0.00 => corresponds to 0.02 % core utilization over time interval
  129. ----------------------------------------------------------------------------------------------
  130.  
  131. ----------------------------------------------------------------------------------------------
  132. SKT 0 package consumed 3.35 Joules
  133. ----------------------------------------------------------------------------------------------
  134. TOTAL: 3.35 Joules
  135.  
  136. EXEC : instructions per nominal CPU cycle
  137. IPC : instructions per CPU cycle
  138. FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost)
  139. AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost)
  140. L3MISS: L3 cache misses
  141. L2MISS: L2 cache misses (including other core's L2 cache *hits*)
  142. L3HIT : L3 cache hit ratio (0.00-1.00)
  143. L2HIT : L2 cache hit ratio (0.00-1.00)
  144. L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency
  145. L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00)
  146. READ : bytes read from memory controller (in GBytes)
  147. WRITE : bytes written to memory controller (in GBytes)
  148. IO : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests
  149. TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature
  150.  
  151.  
  152. Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE | IO | TEMP |
  153.  
  154. 0 0 0.00 0.23 0.00 0.55 24 K 25 K 0.06 0.01 1.04 0.01 N/A N/A N/A 70
  155. 1 0 0.00 0.23 0.00 0.55 7488 7778 0.04 0.01 1.45 0.02 N/A N/A N/A 70
  156. 2 0 0.00 0.48 0.00 0.55 7043 7290 0.03 0.00 1.03 0.01 N/A N/A N/A 70
  157. 3 0 0.00 0.22 0.00 0.55 6712 7011 0.04 0.00 1.39 0.01 N/A N/A N/A 70
  158. 4 0 0.00 0.21 0.00 0.55 47 K 53 K 0.11 0.00 1.37 0.03 N/A N/A N/A 70
  159. 5 0 0.00 0.30 0.00 0.55 12 K 13 K 0.03 0.07 1.30 0.01 N/A N/A N/A 70
  160. 6 0 0.00 0.34 0.00 0.55 24 K 26 K 0.09 0.00 0.99 0.02 N/A N/A N/A 70
  161. 7 0 0.00 0.51 0.00 0.55 11 K 11 K 0.02 0.03 1.13 0.00 N/A N/A N/A 70
  162. -----------------------------------------------------------------------------------------------------------------------------
  163. SKT 0 0.00 0.29 0.00 0.55 141 K 152 K 0.07 0.01 1.19 0.02 0.37 0.00 0.36 70
  164. -----------------------------------------------------------------------------------------------------------------------------
  165. TOTAL * 0.00 0.29 0.00 0.55 141 K 152 K 0.07 0.01 1.19 0.02 0.37 0.00 0.36 N/A
  166.  
  167. Instructions retired: 6239 K ; Active cycles: 21 M ; Time (TSC): 2330 Mticks ; C0 (active,non-halted) core residency: 0.21 %
  168.  
  169. C1 core residency: 0.26 %; C3 core residency: 0.00 %; C6 core residency: 0.00 %; C7 core residency: 99.53 %;
  170. C2 package residency: 1.04 %; C3 package residency: 0.00 %; C6 package residency: 0.61 %; C7 package residency: 96.72 %;
  171.  
  172. PHYSICAL CORE IPC : 0.58 => corresponds to 14.51 % utilization for cores in active state
  173. Instructions per nominal CPU cycle: 0.00 => corresponds to 0.02 % core utilization over time interval
  174. ----------------------------------------------------------------------------------------------
  175.  
  176. ----------------------------------------------------------------------------------------------
  177. SKT 0 package consumed 3.33 Joules
  178. ----------------------------------------------------------------------------------------------
  179. TOTAL: 3.33 Joules
  180.  
  181. EXEC : instructions per nominal CPU cycle
  182. IPC : instructions per CPU cycle
  183. FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost)
  184. AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost)
  185. L3MISS: L3 cache misses
  186. L2MISS: L2 cache misses (including other core's L2 cache *hits*)
  187. L3HIT : L3 cache hit ratio (0.00-1.00)
  188. L2HIT : L2 cache hit ratio (0.00-1.00)
  189. L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency
  190. L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00)
  191. READ : bytes read from memory controller (in GBytes)
  192. WRITE : bytes written to memory controller (in GBytes)
  193. IO : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests
  194. TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature
  195.  
  196.  
  197. Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE | IO | TEMP |
  198.  
  199. 0 0 0.00 0.36 0.00 0.55 33 K 35 K 0.07 0.20 1.02 0.02 N/A N/A N/A 75
  200. 1 0 0.00 0.29 0.00 0.55 10 K 11 K 0.11 0.01 1.32 0.04 N/A N/A N/A 75
  201. 2 0 0.00 0.51 0.00 0.55 6588 6874 0.04 0.00 1.02 0.01 N/A N/A N/A 75
  202. 3 0 0.00 0.38 0.00 0.55 12 K 13 K 0.06 0.07 1.68 0.02 N/A N/A N/A 75
  203. 4 0 0.00 0.23 0.00 0.55 46 K 52 K 0.11 0.00 1.16 0.03 N/A N/A N/A 75
  204. 5 0 0.00 0.31 0.00 0.55 13 K 14 K 0.02 0.07 1.41 0.01 N/A N/A N/A 75
  205. 6 0 0.00 0.34 0.00 0.55 24 K 26 K 0.08 0.00 0.99 0.02 N/A N/A N/A 75
  206. 7 0 0.00 0.57 0.00 0.55 18 K 19 K 0.02 0.18 1.14 0.00 N/A N/A N/A 75
  207. -----------------------------------------------------------------------------------------------------------------------------
  208. SKT 0 0.00 0.34 0.00 0.55 166 K 179 K 0.07 0.08 1.14 0.02 0.38 0.00 0.36 74
  209. -----------------------------------------------------------------------------------------------------------------------------
  210. TOTAL * 0.00 0.34 0.00 0.55 166 K 179 K 0.07 0.08 1.14 0.02 0.38 0.00 0.36 N/A
  211.  
  212. Instructions retired: 8995 K ; Active cycles: 26 M ; Time (TSC): 2335 Mticks ; C0 (active,non-halted) core residency: 0.26 %
  213.  
  214. C1 core residency: 0.32 %; C3 core residency: 0.00 %; C6 core residency: 0.00 %; C7 core residency: 99.43 %;
  215. C2 package residency: 1.09 %; C3 package residency: 0.00 %; C6 package residency: 0.60 %; C7 package residency: 96.31 %;
  216.  
  217. PHYSICAL CORE IPC : 0.69 => corresponds to 17.18 % utilization for cores in active state
  218. Instructions per nominal CPU cycle: 0.00 => corresponds to 0.02 % core utilization over time interval
  219. ----------------------------------------------------------------------------------------------
  220.  
  221. ----------------------------------------------------------------------------------------------
  222. SKT 0 package consumed 3.35 Joules
  223. ----------------------------------------------------------------------------------------------
  224. TOTAL: 3.35 Joules
  225.  
  226. EXEC : instructions per nominal CPU cycle
  227. IPC : instructions per CPU cycle
  228. FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost)
  229. AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost)
  230. L3MISS: L3 cache misses
  231. L2MISS: L2 cache misses (including other core's L2 cache *hits*)
  232. L3HIT : L3 cache hit ratio (0.00-1.00)
  233. L2HIT : L2 cache hit ratio (0.00-1.00)
  234. L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency
  235. L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00)
  236. READ : bytes read from memory controller (in GBytes)
  237. WRITE : bytes written to memory controller (in GBytes)
  238. IO : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests
  239. TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature
  240.  
  241.  
  242. Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE | IO | TEMP |
  243.  
  244. 0 0 0.00 0.23 0.00 0.55 26 K 30 K 0.11 0.01 1.27 0.03 N/A N/A N/A 75
  245. 1 0 0.00 0.22 0.00 0.55 7048 7287 0.03 0.00 1.52 0.01 N/A N/A N/A 75
  246. 2 0 0.00 0.28 0.00 0.55 8310 9155 0.09 0.02 0.70 0.01 N/A N/A N/A 75
  247. 3 0 0.00 0.38 0.00 0.55 7410 7911 0.06 0.00 1.26 0.02 N/A N/A N/A 75
  248. 4 0 0.00 0.23 0.00 0.55 48 K 54 K 0.10 0.00 1.36 0.03 N/A N/A N/A 75
  249. 5 0 0.00 0.32 0.00 0.55 13 K 14 K 0.02 0.08 0.90 0.01 N/A N/A N/A 75
  250. 6 0 0.00 0.33 0.00 0.55 18 K 20 K 0.09 0.00 0.99 0.02 N/A N/A N/A 75
  251. 7 0 0.00 0.50 0.00 0.55 17 K 18 K 0.02 0.06 1.32 0.01 N/A N/A N/A 75
  252. -----------------------------------------------------------------------------------------------------------------------------
  253. SKT 0 0.00 0.29 0.00 0.55 148 K 161 K 0.08 0.02 1.17 0.02 0.37 0.00 0.36 75
  254. -----------------------------------------------------------------------------------------------------------------------------
  255. TOTAL * 0.00 0.29 0.00 0.55 148 K 161 K 0.08 0.02 1.17 0.02 0.37 0.00 0.36 N/A
  256.  
  257. Instructions retired: 6764 K ; Active cycles: 22 M ; Time (TSC): 2335 Mticks ; C0 (active,non-halted) core residency: 0.23 %
  258.  
  259. C1 core residency: 0.28 %; C3 core residency: 0.00 %; C6 core residency: 0.00 %; C7 core residency: 99.49 %;
  260. C2 package residency: 1.05 %; C3 package residency: 0.00 %; C6 package residency: 0.53 %; C7 package residency: 96.67 %;
  261.  
  262. PHYSICAL CORE IPC : 0.59 => corresponds to 14.74 % utilization for cores in active state
  263. Instructions per nominal CPU cycle: 0.00 => corresponds to 0.02 % core utilization over time interval
  264. ----------------------------------------------------------------------------------------------
  265.  
  266. ----------------------------------------------------------------------------------------------
  267. SKT 0 package consumed 3.34 Joules
  268. ----------------------------------------------------------------------------------------------
  269. TOTAL: 3.34 Joules
  270.  
  271. EXEC : instructions per nominal CPU cycle
  272. IPC : instructions per CPU cycle
  273. FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost)
  274. AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost)
  275. L3MISS: L3 cache misses
  276. L2MISS: L2 cache misses (including other core's L2 cache *hits*)
  277. L3HIT : L3 cache hit ratio (0.00-1.00)
  278. L2HIT : L2 cache hit ratio (0.00-1.00)
  279. L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency
  280. L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00)
  281. READ : bytes read from memory controller (in GBytes)
  282. WRITE : bytes written to memory controller (in GBytes)
  283. IO : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests
  284. TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature
  285.  
  286.  
  287. Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE | IO | TEMP |
  288.  
  289. 0 0 0.00 0.29 0.00 0.55 45 K 57 K 0.21 0.01 0.96 0.06 N/A N/A N/A 72
  290. 1 0 0.00 0.23 0.00 0.55 7925 8225 0.04 0.01 1.63 0.01 N/A N/A N/A 72
  291. 2 0 0.00 0.33 0.00 0.55 5853 6971 0.16 0.00 0.76 0.03 N/A N/A N/A 69
  292. 3 0 0.00 0.22 0.00 0.55 8456 9438 0.10 0.00 1.21 0.03 N/A N/A N/A 69
  293. 4 0 0.00 0.22 0.00 0.55 46 K 53 K 0.13 0.00 1.24 0.04 N/A N/A N/A 69
  294. 5 0 0.00 0.31 0.00 0.55 12 K 12 K 0.05 0.08 1.17 0.01 N/A N/A N/A 69
  295. 6 0 0.00 0.27 0.00 0.55 3968 4161 0.05 0.00 0.86 0.01 N/A N/A N/A 68
  296. 7 0 0.00 0.55 0.00 0.55 8275 8631 0.04 0.03 0.86 0.01 N/A N/A N/A 68
  297. -----------------------------------------------------------------------------------------------------------------------------
  298. SKT 0 0.00 0.28 0.00 0.55 138 K 160 K 0.14 0.01 1.08 0.04 0.37 0.00 0.36 68
  299. -----------------------------------------------------------------------------------------------------------------------------
  300. TOTAL * 0.00 0.28 0.00 0.55 138 K 160 K 0.14 0.01 1.08 0.04 0.37 0.00 0.36 N/A
  301.  
  302. Instructions retired: 6593 K ; Active cycles: 23 M ; Time (TSC): 2335 Mticks ; C0 (active,non-halted) core residency: 0.23 %
  303.  
  304. C1 core residency: 0.30 %; C3 core residency: 0.49 %; C6 core residency: 0.00 %; C7 core residency: 98.99 %;
  305. C2 package residency: 1.35 %; C3 package residency: 0.34 %; C6 package residency: 0.50 %; C7 package residency: 96.13 %;
  306.  
  307. PHYSICAL CORE IPC : 0.57 => corresponds to 14.22 % utilization for cores in active state
  308. Instructions per nominal CPU cycle: 0.00 => corresponds to 0.02 % core utilization over time interval
  309. ----------------------------------------------------------------------------------------------
  310.  
  311. ----------------------------------------------------------------------------------------------
  312. SKT 0 package consumed 3.35 Joules
  313. ----------------------------------------------------------------------------------------------
  314. TOTAL: 3.35 Joules
  315.  
  316. EXEC : instructions per nominal CPU cycle
  317. IPC : instructions per CPU cycle
  318. FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost)
  319. AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost)
  320. L3MISS: L3 cache misses
  321. L2MISS: L2 cache misses (including other core's L2 cache *hits*)
  322. L3HIT : L3 cache hit ratio (0.00-1.00)
  323. L2HIT : L2 cache hit ratio (0.00-1.00)
  324. L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency
  325. L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00)
  326. READ : bytes read from memory controller (in GBytes)
  327. WRITE : bytes written to memory controller (in GBytes)
  328. IO : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests
  329. TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature
  330.  
  331.  
  332. Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE | IO | TEMP |
  333.  
  334. 0 0 0.00 0.25 0.00 0.55 24 K 27 K 0.11 0.01 0.97 0.03 N/A N/A N/A 70
  335. 1 0 0.00 0.24 0.00 0.55 7466 7726 0.03 0.00 1.37 0.01 N/A N/A N/A 70
  336. 2 0 0.00 0.47 0.00 0.55 7482 7835 0.05 0.00 1.05 0.01 N/A N/A N/A 70
  337. 3 0 0.00 0.22 0.00 0.55 6732 6957 0.03 0.00 1.43 0.01 N/A N/A N/A 70
  338. 4 0 0.00 0.21 0.00 0.55 45 K 51 K 0.12 0.00 1.33 0.03 N/A N/A N/A 70
  339. 5 0 0.00 0.33 0.00 0.55 10 K 11 K 0.03 0.09 1.27 0.01 N/A N/A N/A 70
  340. 6 0 0.00 0.33 0.00 0.55 20 K 22 K 0.09 0.00 0.95 0.02 N/A N/A N/A 70
  341. 7 0 0.00 0.49 0.00 0.55 12 K 13 K 0.01 0.03 1.17 0.00 N/A N/A N/A 70
  342. -----------------------------------------------------------------------------------------------------------------------------
  343. SKT 0 0.00 0.29 0.00 0.55 135 K 148 K 0.08 0.01 1.15 0.02 0.37 0.00 0.36 70
  344. -----------------------------------------------------------------------------------------------------------------------------
  345. TOTAL * 0.00 0.29 0.00 0.55 135 K 148 K 0.08 0.01 1.15 0.02 0.37 0.00 0.36 N/A
  346.  
  347. Instructions retired: 6227 K ; Active cycles: 21 M ; Time (TSC): 2335 Mticks ; C0 (active,non-halted) core residency: 0.21 %
  348.  
  349. C1 core residency: 0.26 %; C3 core residency: 0.00 %; C6 core residency: 0.00 %; C7 core residency: 99.53 %;
  350. C2 package residency: 1.14 %; C3 package residency: 0.00 %; C6 package residency: 0.61 %; C7 package residency: 96.62 %;
  351.  
  352. PHYSICAL CORE IPC : 0.59 => corresponds to 14.66 % utilization for cores in active state
  353. Instructions per nominal CPU cycle: 0.00 => corresponds to 0.02 % core utilization over time interval
  354. ----------------------------------------------------------------------------------------------
  355.  
  356. ----------------------------------------------------------------------------------------------
  357. SKT 0 package consumed 3.34 Joules
  358. ----------------------------------------------------------------------------------------------
  359. TOTAL: 3.34 Joules
  360.  
  361. EXEC : instructions per nominal CPU cycle
  362. IPC : instructions per CPU cycle
  363. FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost)
  364. AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost)
  365. L3MISS: L3 cache misses
  366. L2MISS: L2 cache misses (including other core's L2 cache *hits*)
  367. L3HIT : L3 cache hit ratio (0.00-1.00)
  368. L2HIT : L2 cache hit ratio (0.00-1.00)
  369. L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency
  370. L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00)
  371. READ : bytes read from memory controller (in GBytes)
  372. WRITE : bytes written to memory controller (in GBytes)
  373. IO : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests
  374. TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature
  375.  
  376.  
  377. Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE | IO | TEMP |
  378.  
  379. 0 0 0.00 0.23 0.00 0.55 21 K 23 K 0.08 0.01 1.00 0.02 N/A N/A N/A 75
  380. 1 0 0.00 0.29 0.00 0.55 4206 4322 0.03 0.01 1.71 0.01 N/A N/A N/A 75
  381. 2 0 0.00 0.52 0.00 0.55 6786 7009 0.03 0.00 1.17 0.01 N/A N/A N/A 75
  382. 3 0 0.00 0.22 0.00 0.55 7329 7673 0.04 0.00 1.63 0.02 N/A N/A N/A 75
  383. 4 0 0.00 0.21 0.00 0.55 45 K 51 K 0.12 0.00 1.39 0.04 N/A N/A N/A 75
  384. 5 0 0.00 0.33 0.00 0.55 11 K 11 K 0.03 0.09 1.39 0.01 N/A N/A N/A 75
  385. 6 0 0.00 0.34 0.00 0.55 23 K 26 K 0.09 0.00 0.99 0.02 N/A N/A N/A 75
  386. 7 0 0.00 0.62 0.00 0.55 11 K 11 K 0.01 0.07 1.22 0.00 N/A N/A N/A 75
  387. -----------------------------------------------------------------------------------------------------------------------------
  388. SKT 0 0.00 0.30 0.00 0.55 131 K 143 K 0.08 0.02 1.22 0.02 0.37 0.00 0.36 74
  389. -----------------------------------------------------------------------------------------------------------------------------
  390. TOTAL * 0.00 0.30 0.00 0.55 131 K 143 K 0.08 0.02 1.22 0.02 0.37 0.00 0.36 N/A
  391.  
  392. Instructions retired: 5917 K ; Active cycles: 19 M ; Time (TSC): 2335 Mticks ; C0 (active,non-halted) core residency: 0.19 %
  393.  
  394. C1 core residency: 0.25 %; C3 core residency: 0.00 %; C6 core residency: 0.00 %; C7 core residency: 99.56 %;
  395. C2 package residency: 1.15 %; C3 package residency: 0.00 %; C6 package residency: 0.63 %; C7 package residency: 96.61 %;
  396.  
  397. PHYSICAL CORE IPC : 0.61 => corresponds to 15.18 % utilization for cores in active state
  398. Instructions per nominal CPU cycle: 0.00 => corresponds to 0.02 % core utilization over time interval
  399. ----------------------------------------------------------------------------------------------
  400.  
  401. ----------------------------------------------------------------------------------------------
  402. SKT 0 package consumed 3.33 Joules
  403. ----------------------------------------------------------------------------------------------
  404. TOTAL: 3.33 Joules
  405. ^CDEBUG: caught signal to interrupt (Interrupt).
  406. Cleaning up
  407. Zeroed PMU registers
  408. Freeing up all RMIDs
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