process(Clock)
begin
    if (Reset = '1') then
        MainFSM_State       <= ST_IDLE;
        Func1FSM_State  <= ST_IDLE;
        Func2FSM_State  <= ST_IDLE;
    else
        MainFSM_State       <= MainFSM_NextState;
        Func1FSM_State  <= Func1FSM_NextState;
        Func2FSM_State  <= Func2FSM_NextState;
    end if;
end process;

process(MainFSM_State, Input, ...,
                Func1FSM_Output, Func1FSM_Return,
                Func2FSM_Output, Func2FSM_Return)
begin
    Func1FSM_Call           <= '0';
    Func2FSM_Call           <= '0';

    MainFSM_Output      <= x"00";

    case MainFSM_State is
        when ST_IDLE =>
            if (Input = '1') then
                Func1FSM_Call               <= '1';
                MainFSM_NextState       <= ST_FUNC1_EXECUTING;
            end if;

        when ST_FUNC1_EXECUTING =>
            MainFSM_Output              <= Func1FSM_Output;

            if (Func1FSM_Return = '1') then
                Func2FSM_Call               <= '1';
            end if;

       ....
    end case;
end process;