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By: a guest on Jul 28th, 2010  |  syntax: C  |  size: 1.15 KB  |  views: 18  |  expires: Never
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  1.   /* wait for reset */
  2.   while((AT91C_BASE_RSTC->RSTC_RSR & (AT91C_RSTC_SRCMP | AT91C_RSTC_NRSTL)) != AT91C_RSTC_NRSTL)
  3.     ;
  4.   /* enable reset */
  5.   AT91C_BASE_RSTC->RSTC_RMR = ((0xA5 << 24) | AT91C_RSTC_URSTEN);
  6.  
  7.   /* Flash Memory: 1 wait state, about 50 cycles in a microsecond.*/
  8.   AT91C_BASE_MC->MC_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS;
  9.  
  10.   /* Enables the main oscillator and waits 56 slow cycles as startup time.*/
  11.   AT91C_BASE_PMC->PMC_MOR = (AT91C_CKGR_OSCOUNT & (7 << 8)) | AT91C_CKGR_MOSCEN;
  12.   while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS))
  13.     ;
  14.  
  15.   /* PLL setup: DIV = 14, MUL = 72, PLLCOUNT = 10
  16.      PLLfreq = 96109714 Hz (rounded).*/
  17.   AT91C_BASE_PMC->PMC_PLLR = (AT91C_CKGR_DIV & 14) |
  18.                              (AT91C_CKGR_PLLCOUNT & (10 << 8)) |
  19.                              (AT91C_CKGR_USBDIV_1) |
  20.                              (AT91C_CKGR_MUL & (72 << 16));
  21.   while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK))
  22.     ;
  23.  
  24.   /* Master clock = PLLfreq / 2 = 48054858 Hz (rounded).*/
  25.   AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2;
  26.   while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY))
  27.     ;