Fixed

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    17:59:53 11/20/2014
-- Design Name:
-- Module Name:    Modul - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Modul is
    Port ( iSEL : in  STD_LOGIC_VECTOR (1 downto 0);
           iA : in  STD_LOGIC_VECTOR (7 downto 0);
              oY : out  STD_LOGIC_VECTOR (1 downto 0)
            );
end Modul;

architecture Behavioral of Modul is

-- Izlazi iz DEMUXa
signal sDLL, sDLD, sDAL, sDAD: STD_LOGIC_VECTOR(7 downto 0) := (others => '0');

-- Izlazi iz pomjeraca
signal sDLL1, sDLD1, sDAL1, sDAD1: STD_LOGIC_VECTOR(7 downto 0);

begin


    --process(iSEL, iA) begin
        sDLL <= iA when (iSEL = "00") else (others => '0');
        sDLD <= iA when (iSEL = "01") else (others => '0');
        sDAL <= iA when (iSEL = "10") else (others => '0');
        sDAD <= iA when (iSEL = "11") else (others => '0');
    --end process;

    -- Ovo mozda ne bi bilo lose razdvojiti po procesima
    process (sDLL, sDLD, sDAL, sDAD) begin
        sDLL1 <= sDLL(6 downto 0) & '0';
        sDLD1 <= '0' & sDLD(7 downto 1);
        sDAL1 <= sDAL(7) & sDAL(5 downto 0) & '0';
        sDAD1 <= sDAD(7) & '0' & sDAD(7 downto 2);
    end process;

    -- Koder
    process (sDLL1, sDLD1, sDAL1, sDAD1) begin
        if (not (sDLL1 = 0)) then
            oY <= "00";
        elsif (not (sDLD1 = 0)) then
            oY <= "01";
        elsif (not (sDAL1 = 0)) then
            oY <= "10";
        else
            oY <= "11";
        end if;
    end process;
end Behavioral;