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  1. diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
  2. index 7242b7f..1ff1f47 100644
  3. --- a/arch/arm/mach-msm/Kconfig
  4. +++ b/arch/arm/mach-msm/Kconfig
  5. @@ -1067,6 +1067,42 @@ config PHYS_OFFSET
  6.         depends on MACH_HTCLEO
  7.         default "0x11800000" if MACH_HTCLEO
  8.  
  9. +config HTCLEO_CPU_VOLT
  10. +        bool
  11. +        default y if HTCLEO_NO_UNDERVOLT
  12. +
  13. +choice
  14. +   prompt "The minimum amount of voltage feeds into the CPU is"
  15. +
  16. +   default HTCLEO_NO_UNDERVOLT
  17. +
  18. +   config HTCLEO_UNDERVOLT_1000
  19. +       bool "1000 mV"
  20. +
  21. +   config HTCLEO_UNDERVOLT_925
  22. +       bool "925 mV"
  23. +
  24. +   config HTCLEO_UNDERVOLT_800
  25. +       bool "800 mV - does not work on every device"
  26. +
  27. +   config HTCLEO_NO_UNDERVOLT
  28. +       bool "DEFAULT - 1050mV"
  29. +
  30. +endchoice
  31. +      
  32. +config HTCLEO_OVERCLOCK
  33. +  bool "Support overclock to 1.113GHz"
  34. +   default n
  35. +  help
  36. +       add overclock ability to 1.113GHz.
  37. +config HTCLEO_EXOVERCLOCK
  38. +  bool "Support overclock to 1.305GHz"
  39. +   depends on HTCLEO_OVERCLOCK
  40. +   default n
  41. +  help
  42. +       add overclock ability to 1.305GHz.
  43. +
  44. +
  45.  config HTC_FB_CONSOLE
  46.     bool "Boot console for HTC phones (needs a font which has width <= 8)"
  47.     default n
  48. diff --git a/arch/arm/mach-msm/acpuclock-scorpion.c b/arch/arm/mach-msm/acpuclock-scorpion.c
  49. index 44e9b60..e87e643 100644
  50. --- a/arch/arm/mach-msm/acpuclock-scorpion.c
  51. +++ b/arch/arm/mach-msm/acpuclock-scorpion.c
  52. @@ -73,6 +73,75 @@ struct clkctl_acpu_speed {
  53.  #define SRC_PLL1   3 /* 768 MHz */
  54.  
  55.  struct clkctl_acpu_speed acpu_freq_tbl[] = {
  56. +#ifdef CONFIG_HTCLEO_UNDERVOLT_1000
  57. +   {  19200, CCTL(CLK_TCXO, 1),        SRC_RAW, 0, 0, 1000, 14000 },
  58. +   { 128000, CCTL(CLK_TCXO, 1),        SRC_AXI, 0, 0, 1000, 14000 },
  59. +   { 245000, CCTL(CLK_MODEM_PLL, 1),   SRC_RAW, 0, 0, 1000, 29000 },
  60. +   //{ 256000, CCTL(CLK_GLOBAL_PLL, 3),    SRC_RAW, 0, 0, 1000, 29000 },
  61. +   { 384000, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x0A, 0, 1000, 58000 },
  62. +   { 422400, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x0B, 0, 1000, 117000 },
  63. +   { 460800, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x0C, 0, 1000, 117000 },
  64. +   { 499200, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x0D, 0, 1025, 117000 },
  65. +   { 537600, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x0E, 0, 1050, 117000 },
  66. +   { 576000, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x0F, 0, 1050, 117000 },
  67. +   { 614400, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x10, 0, 1075, 117000 },
  68. +   { 652800, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x11, 0, 1100, 117000 },
  69. +   { 691200, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x12, 0, 1125, 117000 },
  70. +   { 729600, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x13, 0, 1150, 117000 },
  71. +   { 768000, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x14, 0, 1150, 128000 },
  72. +   { 806400, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x15, 0, 1175, 128000 },
  73. +   { 844800, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x16, 0, 1200, 128000 },
  74. +   { 883200, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x17, 0, 1200, 128000 },
  75. +   { 921600, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x18, 0, 1225, 128000 },
  76. +   { 960000, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x19, 0, 1225, 128000 },
  77. +   { 998400, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x1A, 0, 1225, 128000 },
  78. +#elif CONFIG_HTCLEO_UNDERVOLT_925
  79. +   // should work with most of HD2s
  80. +   {  19200, CCTL(CLK_TCXO, 1),        SRC_RAW, 0, 0, 925, 14000 },
  81. +   { 128000, CCTL(CLK_TCXO, 1),        SRC_AXI, 0, 0, 925, 14000 },
  82. +   { 245000, CCTL(CLK_MODEM_PLL, 1),   SRC_RAW, 0, 0, 925, 29000 },
  83. +   //{ 256000, CCTL(CLK_GLOBAL_PLL, 3),    SRC_RAW, 0, 0, 925, 29000 },
  84. +   { 384000, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x0A, 0, 950, 58000 },
  85. +   { 422400, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x0B, 0, 975, 117000 },
  86. +   { 460800, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x0C, 0, 1000, 117000 },
  87. +   { 499200, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x0D, 0, 1025, 117000 },
  88. +   { 537600, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x0E, 0, 1050, 117000 },
  89. +   { 576000, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x0F, 0, 1050, 117000 },
  90. +   { 614400, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x10, 0, 1075, 117000 },
  91. +   { 652800, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x11, 0, 1100, 117000 },
  92. +   { 691200, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x12, 0, 1125, 117000 },
  93. +   { 729600, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x13, 0, 1150, 117000 },
  94. +   { 768000, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x14, 0, 1150, 128000 },
  95. +   { 806400, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x15, 0, 1175, 128000 },
  96. +   { 844800, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x16, 0, 1200, 128000 },
  97. +   { 883200, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x17, 0, 1200, 128000 },
  98. +   { 921600, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x18, 0, 1225, 128000 },
  99. +   { 960000, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x19, 0, 1225, 128000 },
  100. +   { 998400, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x1A, 0, 1225, 128000 },
  101. +#elif CONFIG_HTCLEO_UNDERVOLT_800
  102. +   // not working yet
  103. +   {  19200, CCTL(CLK_TCXO, 1),        SRC_RAW, 0, 0, 850, 14000 },
  104. +   { 128000, CCTL(CLK_TCXO, 1),        SRC_AXI, 0, 0, 850, 14000 },
  105. +   { 245000, CCTL(CLK_MODEM_PLL, 1),   SRC_RAW, 0, 0, 850, 29000 },
  106. +   //{ 256000, CCTL(CLK_GLOBAL_PLL, 3),    SRC_RAW, 0, 0, 850, 29000 },
  107. +   { 384000, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x0A, 0, 850, 58000 },
  108. +   { 422400, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x0B, 0, 875, 117000 },
  109. +   { 460800, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x0C, 0, 900, 117000 },
  110. +   { 499200, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x0D, 0, 925, 117000 },
  111. +   { 537600, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x0E, 0, 950, 117000 },
  112. +   { 576000, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x0F, 0, 950, 117000 },
  113. +   { 614400, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x10, 0, 975, 117000 },
  114. +   { 652800, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x11, 0, 1000, 117000 },
  115. +   { 691200, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x12, 0, 1025, 117000 },
  116. +   { 729600, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x13, 0, 1050, 117000 },
  117. +   { 768000, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x14, 0, 1125, 128000 },
  118. +   { 806400, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x15, 0, 1125, 128000 },
  119. +   { 844800, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x16, 0, 1150, 128000 },
  120. +   { 883200, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x17, 0, 1150, 128000 },
  121. +   { 921600, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x18, 0, 1175, 128000 },
  122. +   { 960000, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x19, 0, 1175, 128000 },
  123. +   { 998400, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x1A, 0, 1200, 128000 },
  124. +#else
  125.     {  19200, CCTL(CLK_TCXO, 1),        SRC_RAW, 0, 0, 1050, 14000},
  126.     { 128000, CCTL(CLK_TCXO, 1),        SRC_AXI, 0, 0, 1050, 14000 },
  127.     { 245000, CCTL(CLK_MODEM_PLL, 1),   SRC_RAW, 0, 0, 1050, 29000 },
  128. @@ -95,6 +164,30 @@ struct clkctl_acpu_speed acpu_freq_tbl[] = {
  129.     { 921600, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x18, 0, 1300, 128000 },
  130.     { 960000, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x19, 0, 1300, 128000 },
  131.     { 998400, CCTL(CLK_TCXO, 1),        SRC_SCPLL, 0x1A, 0, 1300, 128000 },
  132. +#endif
  133. +#ifdef CONFIG_HTCLEO_OVERCLOCK
  134. +#ifdef CONFIG_HTCLEO_UNDERVOLT_1000
  135. +   { 1036800, CCTL(CLK_TCXO, 1),       SRC_SCPLL, 0x1B, 0, 1225, 128000 },
  136. +   { 1075200, CCTL(CLK_TCXO, 1),       SRC_SCPLL, 0x1C, 0, 1250, 128000 },
  137. +   { 1113600, CCTL(CLK_TCXO, 1),       SRC_SCPLL, 0x1D, 0, 1275, 128000 },
  138. +#elif CONFIG_HTCLEO_UNDERVOLT_925
  139. +   { 1036800, CCTL(CLK_TCXO, 1),       SRC_SCPLL, 0x1B, 0, 1225, 128000 },
  140. +   { 1075200, CCTL(CLK_TCXO, 1),       SRC_SCPLL, 0x1C, 0, 1250, 128000 },
  141. +   { 1113600, CCTL(CLK_TCXO, 1),       SRC_SCPLL, 0x1D, 0, 1275, 128000 },
  142. +#elif CONFIG_HTCLEO_UNDERVOLT_800
  143. +   { 1036800, CCTL(CLK_TCXO, 1),       SRC_SCPLL, 0x1B, 0, 1225, 128000 },
  144. +   { 1075200, CCTL(CLK_TCXO, 1),       SRC_SCPLL, 0x1C, 0, 1250, 128000 },
  145. +   { 1113600, CCTL(CLK_TCXO, 1),       SRC_SCPLL, 0x1D, 0, 1275, 128000 },
  146. +#else
  147. +   { 1036800, CCTL(CLK_TCXO, 1),       SRC_SCPLL, 0x1B, 0, 1300, 128000 },
  148. +   { 1075200, CCTL(CLK_TCXO, 1),       SRC_SCPLL, 0x1C, 0, 1300, 128000 },
  149. +   { 1113600, CCTL(CLK_TCXO, 1),       SRC_SCPLL, 0x1D, 0, 1300, 128000 },
  150. +#endif
  151. +#endif
  152. +#ifdef CONFIG_HTCLEO_EXOVERCLOCK
  153. +   { 1152000, CCTL(CLK_TCXO, 1),       SRC_SCPLL, 0x1E, 0, 1300, 128000 },
  154. +   { 1190400, CCTL(CLK_TCXO, 1),       SRC_SCPLL, 0x1F, 0, 1300, 128000 },
  155. +#endif
  156.     { 0 },
  157.  };
  158.  
  159. @@ -120,9 +213,10 @@ static void __init acpuclk_init_cpufreq_table(void)
  160.         freq_table[i].index = i;
  161.         freq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
  162.  
  163. -       /* Skip speeds using the global pll */
  164. -       if (acpu_freq_tbl[i].acpu_khz == 256000 ||
  165. -               acpu_freq_tbl[i].acpu_khz == 19200)
  166. +       /* Skip speeds we don't want */
  167. +       if (    acpu_freq_tbl[i].acpu_khz == 19200 ||
  168. +           acpu_freq_tbl[i].acpu_khz == 128000 ||
  169. +           acpu_freq_tbl[i].acpu_khz == 256000)
  170.             continue;
  171.  
  172.         vdd = acpu_freq_tbl[i].vdd;
  173. @@ -411,6 +505,8 @@ static int pll_request(unsigned id, unsigned on)
  174.  #define CT_CSR_PHYS             0xA8700000
  175.  #define TCSR_SPARE2_ADDR        (ct_csr_base + 0x60)
  176.  
  177. +/* hastarin - This appears to remove the extra frequencies from the table
  178. +              so only the highest frequency per VDD is available  */
  179.  void __init acpu_freq_tbl_fixup(void)
  180.  {
  181.     void __iomem *ct_csr_base;
  182. @@ -436,6 +532,9 @@ void __init acpu_freq_tbl_fixup(void)
  183.     case 0x30:
  184.     case 0x00:
  185.         max_acpu_khz = 998400;
  186. +#ifdef CONFIG_HTCLEO_OVERCLOCK
  187. +       max_acpu_khz = 1113600;
  188. +#endif
  189.         break;
  190.     case 0x10:
  191.         max_acpu_khz = 1267200;
  192. @@ -485,11 +584,22 @@ static void __init acpuclk_init(void)
  193.      */
  194.     speed = acpu_freq_tbl;
  195.     for (;;) {
  196. +#ifdef CONFIG_HTCLEO_OVERCLOCK
  197. +       if (speed->acpu_khz == 883200)
  198. +           break;
  199. +#else
  200.         if (speed->acpu_khz == 768000)
  201.             break;
  202. +#endif
  203. +#ifdef CONFIG_HTCLEO_OVERCLOCK
  204. +       if (speed->acpu_khz == 0) {
  205. +           pr_err("acpuclk_init: cannot find 883.2MHz\n");
  206. +           BUG();
  207. +#else
  208.         if (speed->acpu_khz == 0) {
  209.             pr_err("acpuclk_init: cannot find 768MHz\n");
  210.             BUG();
  211. +#endif
  212.         }
  213.         speed++;
  214.     }
  215. diff --git a/arch/arm/mach-msm/board-htcleo.c b/arch/arm/mach-msm/board-htcleo.c
  216. index e13205b..b6d271b 100644
  217. --- a/arch/arm/mach-msm/board-htcleo.c
  218. +++ b/arch/arm/mach-msm/board-htcleo.c
  219. @@ -111,8 +111,8 @@ static struct regulator_init_data tps65023_data[5] =
  220.          .constraints =
  221.         {
  222.              .name = "dcdc1", /* VREG_MSMC2_1V29 */
  223. -            .min_uV = 1000000,
  224. -            .max_uV = 1300000,
  225. +            .min_uV = 925000,
  226. +            .max_uV = 1350000,
  227.              .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
  228.          },
  229.          .consumer_supplies = tps65023_dcdc1_supplies,
  230. diff --git a/arch/arm/mach-msm/cpufreq.c b/arch/arm/mach-msm/cpufreq.c
  231. old mode 100644
  232. new mode 100755
  233. index 5317991..3c27bff
  234. --- a/arch/arm/mach-msm/cpufreq.c
  235. +++ b/arch/arm/mach-msm/cpufreq.c
  236. @@ -22,6 +22,12 @@
  237.  #include <linux/init.h>
  238.  #include "acpuclock.h"
  239.  
  240. +/* Make sure the kernel is not overclocked on boot to avoid potential freezing/boot loops
  241. +* for people with less capable hardware. */
  242. +//#define CPUFREQ_MAX 998400  max should be default freq
  243. +//#define CPUFREQ_MIN 245000  min should be the lowest freq in the table
  244. +
  245. +
  246.  #ifdef CONFIG_MSM_CPU_FREQ_SCREEN
  247.  static void msm_early_suspend(struct early_suspend *handler) {
  248.     acpuclk_set_rate(CONFIG_MSM_CPU_FREQ_SCREEN_OFF * 1000, 0);
  249. @@ -90,6 +96,11 @@ static int __init msm_cpufreq_init(struct cpufreq_policy *policy)
  250.  
  251.     BUG_ON(cpufreq_frequency_table_cpuinfo(policy, table));
  252.     policy->cur = acpuclk_get_rate();
  253. +  
  254. +   /* CPU Clock limitation
  255. +   policy->max = CPUFREQ_MAX;
  256. +   policy->min = CPUFREQ_MIN;*/
  257. +  
  258.     policy->cpuinfo.transition_latency =
  259.         acpuclk_get_switch_time() * NSEC_PER_USEC;
  260.     return 0;
  261. diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
  262. index ca7b088..d239415 100644
  263. --- a/drivers/cpufreq/Kconfig
  264. +++ b/drivers/cpufreq/Kconfig
  265. @@ -111,6 +111,13 @@ config CPU_FREQ_DEFAULT_GOV_CONSERVATIVE
  266.       governor. If unsure have a look at the help section of the
  267.       driver. Fallback governor will be the performance governor.
  268.  
  269. +config CPU_FREQ_DEFAULT_GOV_SMARTASS
  270. +   bool "smartass"
  271. +   select CPU_FREQ_GOV_SMARTASS
  272. +   select CPU_FREQ_GOV_PERFORMANCE
  273. +   help
  274. +     Use the CPUFreq governor 'smartass' as default.
  275. +
  276.  config CPU_FREQ_DEFAULT_GOV_INTERACTIVE
  277.     bool "interactive"
  278.     select CPU_FREQ_GOV_INTERACTIVE
  279. @@ -205,4 +212,12 @@ config CPU_FREQ_GOV_CONSERVATIVE
  280.  
  281.       If in doubt, say N.
  282.  
  283. +config CPU_FREQ_GOV_SMARTASS
  284. +      tristate "'smartass' cpufreq governor"
  285. +      depends on CPU_FREQ
  286. +      help
  287. +        'smartass' - a "smart" optimized governor for the hero!
  288. +        If in doubt, say N.
  289. +
  290. +
  291.  endif  # CPU_FREQ
  292. diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
  293. index 30629f7..925dfd5 100644
  294. --- a/drivers/cpufreq/Makefile
  295. +++ b/drivers/cpufreq/Makefile
  296. @@ -10,6 +10,7 @@ obj-$(CONFIG_CPU_FREQ_GOV_USERSPACE)  += cpufreq_userspace.o
  297.  obj-$(CONFIG_CPU_FREQ_GOV_ONDEMAND)    += cpufreq_ondemand.o
  298.  obj-$(CONFIG_CPU_FREQ_GOV_CONSERVATIVE)    += cpufreq_conservative.o
  299.  obj-$(CONFIG_CPU_FREQ_GOV_INTERACTIVE) += cpufreq_interactive.o
  300. +obj-$(CONFIG_CPU_FREQ_GOV_SMARTASS)    += cpufreq_smartass.o
  301.  
  302.  # CPUfreq cross-arch helpers
  303.  obj-$(CONFIG_CPU_FREQ_TABLE)       += freq_table.o
  304. diff --git a/drivers/cpufreq/cpufreq_conservative.c b/drivers/cpufreq/cpufreq_conservative.c
  305. index c7b081b..bd3825d 100644
  306. --- a/drivers/cpufreq/cpufreq_conservative.c
  307. +++ b/drivers/cpufreq/cpufreq_conservative.c
  308. @@ -29,8 +29,8 @@
  309.   * It helps to keep variable names smaller, simpler
  310.   */
  311.  
  312. -#define DEF_FREQUENCY_UP_THRESHOLD     (80)
  313. -#define DEF_FREQUENCY_DOWN_THRESHOLD       (20)
  314. +#define DEF_FREQUENCY_UP_THRESHOLD     (65)
  315. +#define DEF_FREQUENCY_DOWN_THRESHOLD       (30)
  316.  
  317.  /*
  318.   * The polling frequency of this governor depends on the capability of
  319. diff --git a/drivers/cpufreq/cpufreq_ondemand.c b/drivers/cpufreq/cpufreq_ondemand.c
  320. index 26e4759..6ee17cb 100644
  321. --- a/drivers/cpufreq/cpufreq_ondemand.c
  322. +++ b/drivers/cpufreq/cpufreq_ondemand.c
  323. @@ -30,11 +30,11 @@
  324.   * It helps to keep variable names smaller, simpler
  325.   */
  326.  
  327. -#define DEF_FREQUENCY_DOWN_DIFFERENTIAL        (10)
  328. -#define DEF_FREQUENCY_UP_THRESHOLD     (80)
  329. +#define DEF_FREQUENCY_DOWN_DIFFERENTIAL        (30)
  330. +#define DEF_FREQUENCY_UP_THRESHOLD     (65)
  331.  #define MICRO_FREQUENCY_DOWN_DIFFERENTIAL  (3)
  332.  #define MICRO_FREQUENCY_UP_THRESHOLD       (95)
  333. -#define MICRO_FREQUENCY_MIN_SAMPLE_RATE        (10000)
  334. +#define MICRO_FREQUENCY_MIN_SAMPLE_RATE        (9500)
  335.  #define MIN_FREQUENCY_UP_THRESHOLD     (11)
  336.  #define MAX_FREQUENCY_UP_THRESHOLD     (100)
  337.  
  338. diff --git a/drivers/i2c/busses/i2c-msm.c b/drivers/i2c/busses/i2c-msm.c
  339. index 62dbc11..59cc801 100644
  340. --- a/drivers/i2c/busses/i2c-msm.c
  341. +++ b/drivers/i2c/busses/i2c-msm.c
  342. @@ -241,13 +241,26 @@ msm_i2c_interrupt(int irq, void *devid)
  343.  
  344.     return IRQ_HANDLED;
  345.  }
  346. +#define MICROP_I2C_RCMD_GSENSOR_X_DATA     0x77
  347. +#define MICROP_I2C_RCMD_GSENSOR_Y_DATA     0x78
  348. +#define MICROP_I2C_RCMD_GSENSOR_Z_DATA     0x79
  349. +#define MICROP_I2C_ADDR                        0x66
  350. +#define GSENSOR_TIMEDOUT                   210
  351. +
  352. +static int is_gsensor_msg(struct i2c_msg msgs[])
  353. +{
  354. +   return msgs->addr==MICROP_I2C_ADDR &&
  355. +                   (msgs->buf[0] == MICROP_I2C_RCMD_GSENSOR_X_DATA ||
  356. +                   msgs->buf[0] == MICROP_I2C_RCMD_GSENSOR_Y_DATA||
  357. +                   msgs->buf[0] == MICROP_I2C_RCMD_GSENSOR_Z_DATA);
  358. +}
  359.  
  360.  static int
  361. -msm_i2c_poll_notbusy(struct msm_i2c_dev *dev, int warn)
  362. +msm_i2c_poll_notbusy(struct msm_i2c_dev *dev, int warn, struct i2c_msg msgs[])
  363.  {
  364.     uint32_t retries = 0;
  365.  
  366. -   while (retries != 200) {
  367. +   while (retries != (is_gsensor_msg(msgs) ? 100 : 200)) {
  368.         uint32_t status = readl(dev->base + I2C_STATUS);
  369.  
  370.         if (!(status & I2C_STATUS_BUS_ACTIVE)) {
  371. @@ -259,8 +272,8 @@ msm_i2c_poll_notbusy(struct msm_i2c_dev *dev, int warn)
  372.         if (retries++ > 100)
  373.             msleep(10);
  374.     }
  375. -   dev_err(dev->dev, "Error waiting for notbusy\n");
  376. -   return -ETIMEDOUT;
  377. +   dev_err(dev->dev, "Error waiting for notbusy (addr=%02x, msgs=%02x)\n", msgs->addr, msgs->buf[0]);
  378. +   return is_gsensor_msg(msgs) ? -GSENSOR_TIMEDOUT : -ETIMEDOUT;
  379.  }
  380.  
  381.  static int
  382. @@ -333,7 +346,7 @@ msm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
  383.  {
  384.     DECLARE_COMPLETION_ONSTACK(complete);
  385.     struct msm_i2c_dev *dev = i2c_get_adapdata(adap);
  386. -   int ret;
  387. +   int ret, ret_wait;
  388.     long timeout;
  389.     unsigned long flags;
  390.  
  391. @@ -346,7 +359,7 @@ msm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
  392.     clk_enable(dev->clk);
  393.     enable_irq(dev->irq);
  394.  
  395. -   ret = msm_i2c_poll_notbusy(dev, 1);
  396. +   ret = msm_i2c_poll_notbusy(dev, 1, msgs);
  397.     if (ret) {
  398.         dev_err(dev->dev, "Still busy in starting xfer(%02X)\n",
  399.             msgs->addr);
  400. @@ -380,9 +393,7 @@ msm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
  401.      */
  402.  
  403.     timeout = wait_for_completion_timeout(&complete, HZ);
  404. -   if (msm_i2c_poll_notbusy(dev, 0))  /* Read may not have stopped in time */
  405. -       dev_err(dev->dev, "Still busy after xfer completion (%02X)\n",
  406. -           msgs->addr);
  407. +   ret_wait = msm_i2c_poll_notbusy(dev, 0, msgs);
  408.     spin_lock_irqsave(&dev->lock, flags);
  409.     if (dev->flush_cnt) {
  410.         dev_warn(dev->dev, "%d unrequested bytes read\n",
  411. @@ -397,7 +408,17 @@ msm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
  412.     dev->flush_cnt = 0;
  413.     dev->cnt = 0;
  414.     spin_unlock_irqrestore(&dev->lock, flags);
  415. -
  416. +   if (ret_wait) /* Read may not have stopped in time */
  417. +   {
  418. +       dev_err(dev->dev, "Still busy after xfer completion (%02X)\n", msgs->addr);
  419. +       if (ret_wait == -GSENSOR_TIMEDOUT)
  420. +           ret = 2; // in most situations the value of ret is 2 (dev->ret), we set it to 2 just to be sure that function i2c_read_block doesn't repeats the read
  421. +       if (!dev->skip_recover) {
  422. +           ret_wait = msm_i2c_recover_bus_busy(dev);
  423. +           if (ret_wait)
  424. +               goto err;
  425. +       }
  426. +   }
  427.     if (!timeout) {
  428.         dev_err(dev->dev, "Transaction timed out\n");
  429.         ret = -ETIMEDOUT;
  430. diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
  431. index 61dca28..5d3c9df 100644
  432. --- a/include/linux/cpufreq.h
  433. +++ b/include/linux/cpufreq.h
  434. @@ -338,6 +338,9 @@ extern struct cpufreq_governor cpufreq_gov_ondemand;
  435.  #elif defined(CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE)
  436.  extern struct cpufreq_governor cpufreq_gov_conservative;
  437.  #define CPUFREQ_DEFAULT_GOVERNOR   (&cpufreq_gov_conservative)
  438. +#elif defined(CONFIG_CPU_FREQ_DEFAULT_GOV_SMARTASS)
  439. +extern struct cpufreq_governor cpufreq_gov_smartass;
  440. +#define CPUFREQ_DEFAULT_GOVERNOR      (&cpufreq_gov_smartass)
  441.  #elif defined(CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE)
  442.  extern struct cpufreq_governor cpufreq_gov_interactive;
  443.  #define CPUFREQ_DEFAULT_GOVERNOR   (&cpufreq_gov_interactive)
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