library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.logic.all;

entity comp is
port (
    SW: in std_logic_vector(1 downto 0);
    LEDR: out std_logic_vector(2 downto 0)
);
end comp;

architecture proc of comp IS
    signal XOR_OUT, AND_OUT, OR_OUT: std_logic;
begin

    LEDR(0) <= func_xor(SW);
    proc_and_or(SW, LEDR(2), LEDR(1));

end proc;