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By: a guest on Jul 13th, 2013  |  syntax: None  |  size: 4.04 KB  |  views: 25  |  expires: Never
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  1. --------------------------------------------------------------------------------
  2. SLURM job 220976 starting up on node mincpld0
  3. --------------------------------------------------------------------------------
  4. job working directory is /nfs/home/azonenberg/Documents/local/programming/achd-soc/trunk/splashbuild/splash/0a2737f233c78b8b8df2ca5b12c12d98ad79d5412221b91c8aefee66cd0fc94e
  5.  
  6. Loading configuration...
  7. Starting jtagd (using ftdi API, interface serial FTWB6M0W) on port 29880...
  8. Spawning test case...
  9. Normal termination of test case
  10. Blanking FPGA for next test...
  11.  
  12. --------------------------------------------------------------------------------
  13. Test case stdout:
  14. --------------------------------------------------------------------------------
  15. Connected to interface "Dev Board JTAG (232H)" (serial number "FTWB6M0W")
  16. Initializing chain...
  17. Scan chain contains 1 devices
  18. Found Xilinx XC2C32A in VQ44 package, stepping 0
  19. Initializing GPIO interface...
  20.     Interface is GPIO capable (12 GPIO pins)
  21. Initializing device...
  22. Generating netlist...
  23. IOB assignment
  24.     IOB for FTDI_GPIOL0 is at fb2_12
  25.     IOB for FTDI_GPIOL1 is at fb2_11
  26.     IOB for LED1 is at fb1_1
  27.     IOB for LED2 is at fb1_2
  28. IO bank fitting
  29. Macrocell fitting
  30.     Pass 1: I/O macrocells                 3 placed, 0 unplaced, 29 available
  31.     Pass 2: Unplaced macrocells            3 placed, 0 unplaced, 29 available
  32. Function block fitting (1)
  33.     Global routing
  34.         1 net(s) assigned to function block inputs
  35.         Pass 1: Greedy assignment          0 unrouted
  36.         Generating ZIA bits
  37.     Product term fitting
  38.         2 pterms used
  39.         Pass 1: Constrained assignment     2 unassigned
  40.         Pass 2: Unconstrained assignment   0 unassigned
  41.     Generating PLA AND array bits
  42.     Generating PLA OR array bits
  43. Function block fitting (2)
  44.     Global routing
  45.         1 net(s) assigned to function block inputs
  46.         Pass 1: Greedy assignment          0 unrouted
  47.         Generating ZIA bits
  48.     Product term fitting
  49.         1 pterms used
  50.         Pass 1: Constrained assignment     1 unassigned
  51.         Pass 2: Unconstrained assignment   0 unassigned
  52.     Generating PLA AND array bits
  53.     Generating PLA OR array bits
  54. Generating bitstream...
  55. Configuring device...
  56.     Using bitstream "Programmer JEDEC Bit Map|Generated on Sat Jul 13 08:49:57 EDT 2013 by azonenberg using libcrowbar|Device: xc2c32a-6-vqg44||" for device "xc2c32a-6-vqg44" (12278 fuses)
  57.     Device xc2c32a, speed 6, package vqg44
  58.     Device name / package check OK
  59.     Erasing device...
  60.     Blank checking...
  61.     Device is blank
  62.     Programming main array (shift register size = 266, nbytes=34)...
  63.     Verifying main array...
  64.     Readback successful
  65.     Testing dout=0
  66.     Testing dout=1
  67.     Testing dout=0
  68.     Testing dout=1
  69.     Testing dout=0
  70.     Testing dout=1
  71.     Testing dout=0
  72.     Testing dout=1
  73.     Testing dout=0
  74.     Testing dout=1
  75.     Testing dout=0
  76.     Testing dout=1
  77.     Testing dout=0
  78.     Testing dout=1
  79.     Testing dout=0
  80.     Testing dout=1
  81.     Testing dout=0
  82.     Testing dout=1
  83.     Testing dout=0
  84.     Testing dout=1
  85. OK
  86.  
  87. --------------------------------------------------------------------------------
  88. jtagd stdout:
  89. --------------------------------------------------------------------------------
  90. JTAG server daemon [SVN rev 1088M] by Andrew D. Zonenberg.
  91.  
  92. License: 3-clause ("new" or "modified") BSD.
  93. This is free software: you are free to change and redistribute it.
  94. There is NO WARRANTY, to the extent permitted by law.
  95.  
  96. Connected to interface "Dev Board JTAG (232H)" (serial number "FTWB6M0W")
  97. Quitting...
  98. Total number of shift operations:       1200
  99. Total number of recoverable errors:     0
  100. Total number of data bits:              57912
  101. Total number of mode bits:              2085
  102. Total number of dummy clocks:           0
  103. Total TCK cycles:                       59997
  104. Total host-side shift time:             145.73 ms
  105. Calculated board-side shift time:       6.00 ms
  106. Calculated total latency:               139.73 ms
  107. Calculated average latency:             0.12 ms