library ieee;
use ieee.std_logic_1164.all;

entity Lab8 is
    port (
        clk: in std_logic;
        t: in std_logic;
        rstn: in std_logic;
        q: out std_logic;
        qn: out std_logic
    );
end Lab8;

architecture behavior of Lab8 is
    signal prev: std_logic;
begin
    process(clk,rstn) begin
        if rstn = '0' then
            prev <= '0';
        elsif clk'EVENT and clk = '1' AND t = '1' then
            prev <= NOT prev;
        end if;
    end process;
    q <= prev;
    qn <= NOT prev;
end behavior;