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  1. Release 14.7 - xst P.20131013 (lin64)
  2. Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
  3. -->
  4. Parameter TMPDIR set to xst/projnav.tmp
  5.  
  6.  
  7. Total REAL time to Xst completion: 0.00 secs
  8. Total CPU time to Xst completion: 0.04 secs
  9.  
  10. -->
  11. Parameter xsthdpdir set to xst
  12.  
  13.  
  14. Total REAL time to Xst completion: 0.00 secs
  15. Total CPU time to Xst completion: 0.04 secs
  16.  
  17. -->
  18. Reading design: orpsoc_top.prj
  19.  
  20. TABLE OF CONTENTS
  21. 1) Synthesis Options Summary
  22. 2) HDL Compilation
  23. 3) Design Hierarchy Analysis
  24. 4) HDL Analysis
  25. 5) HDL Synthesis
  26. 5.1) HDL Synthesis Report
  27. 6) Advanced HDL Synthesis
  28. 6.1) Advanced HDL Synthesis Report
  29. 7) Low Level Synthesis
  30. 8) Partition Report
  31. 9) Final Report
  32. 9.1) Device utilization summary
  33. 9.2) Partition Resource Summary
  34. 9.3) TIMING REPORT
  35.  
  36.  
  37. =========================================================================
  38. * Synthesis Options Summary *
  39. =========================================================================
  40. ---- Source Parameters
  41. Input File Name : "orpsoc_top.prj"
  42. Input Format : mixed
  43. Ignore Synthesis Constraint File : NO
  44.  
  45. ---- Target Parameters
  46. Output File Name : "orpsoc_top"
  47. Output Format : NGC
  48. Target Device : xc3sd1800a-4-fg676
  49.  
  50. ---- Source Options
  51. Top Module Name : orpsoc_top
  52. Automatic FSM Extraction : YES
  53. FSM Encoding Algorithm : Auto
  54. Safe Implementation : No
  55. FSM Style : LUT
  56. RAM Extraction : Yes
  57. RAM Style : Auto
  58. ROM Extraction : Yes
  59. Mux Style : Auto
  60. Decoder Extraction : YES
  61. Priority Encoder Extraction : Yes
  62. Shift Register Extraction : YES
  63. Logical Shifter Extraction : YES
  64. XOR Collapsing : YES
  65. ROM Style : Auto
  66. Mux Extraction : Yes
  67. Resource Sharing : YES
  68. Asynchronous To Synchronous : NO
  69. Use DSP Block : Auto
  70. Automatic Register Balancing : No
  71.  
  72. ---- Target Options
  73. Add IO Buffers : YES
  74. Global Maximum Fanout : 500
  75. Add Generic Clock Buffer(BUFG) : 24
  76. Register Duplication : YES
  77. Slice Packing : YES
  78. Optimize Instantiated Primitives : NO
  79. Use Clock Enable : Yes
  80. Use Synchronous Set : Yes
  81. Use Synchronous Reset : Yes
  82. Pack IO Registers into IOBs : Auto
  83. Equivalent register Removal : YES
  84.  
  85. ---- General Options
  86. Optimization Goal : Speed
  87. Optimization Effort : 1
  88. Keep Hierarchy : No
  89. Netlist Hierarchy : As_Optimized
  90. RTL Output : Yes
  91. Global Optimization : AllClockNets
  92. Read Cores : YES
  93. Write Timing Constraints : NO
  94. Cross Clock Analysis : NO
  95. Hierarchy Separator : /
  96. Bus Delimiter : <>
  97. Case Specifier : Maintain
  98. Slice Utilization Ratio : 100
  99. BRAM Utilization Ratio : 100
  100. DSP48 Utilization Ratio : 100
  101. Verilog 2001 : YES
  102. Auto BRAM Packing : NO
  103. Slice Utilization Ratio Delta : 5
  104.  
  105. =========================================================================
  106.  
  107.  
  108. =========================================================================
  109. * HDL Compilation *
  110. =========================================================================
  111. Compiling verilog file "raminfr.v" in library work
  112. Compiling verilog file "mor1kx_true_dpram_sclk.v" in library work
  113. Module <raminfr> compiled
  114. Compiling verilog file "mor1kx_simple_dpram_sclk.v" in library work
  115. Module <mor1kx_true_dpram_sclk> compiled
  116. Compiling verilog file "mor1kx_cache_lru.v" in library work
  117. Module <mor1kx_simple_dpram_sclk> compiled
  118. Compiling verilog file "uart_tfifo.v" in library work
  119. Compiling verilog include file "uart_defines.v"
  120. Module <mor1kx_cache_lru> compiled
  121. Compiling verilog file "uart_rfifo.v" in library work
  122. Compiling verilog include file "uart_defines.v"
  123. Module <uart_tfifo> compiled
  124. Compiling verilog file "syncflop.v" in library work
  125. Module <uart_rfifo> compiled
  126. Compiling verilog file "mor1kx_ticktimer.v" in library work
  127. Compiling verilog include file "mor1kx-defines.v"
  128. Compiling verilog include file "mor1kx-sprs.v"
  129. Module <syncflop> compiled
  130. Compiling verilog file "mor1kx_store_buffer.v" in library work
  131. Compiling verilog include file "mor1kx-defines.v"
  132. Compiling verilog include file "mor1kx-sprs.v"
  133. Module <mor1kx_ticktimer> compiled
  134. Compiling verilog file "mor1kx_pic.v" in library work
  135. Compiling verilog include file "mor1kx-defines.v"
  136. Compiling verilog include file "mor1kx-sprs.v"
  137. Module <mor1kx_store_buffer> compiled
  138. Compiling verilog file "mor1kx_immu.v" in library work
  139. Compiling verilog include file "mor1kx-defines.v"
  140. Compiling verilog include file "mor1kx-sprs.v"
  141. Module <mor1kx_pic> compiled
  142. ERROR:HDLCompilers:26 - "mor1kx_immu.v" line 278 unexpected token: 'localparam'
  143. ERROR:HDLCompilers:26 - "mor1kx_immu.v" line 278 unexpected token: 'TLB_IDLE'
  144. ERROR:HDLCompilers:26 - "mor1kx_immu.v" line 278 expecting 'endgenerate', found '2'
  145. ERROR:HDLCompilers:28 - "mor1kx_immu.v" line 283 'TLB_IDLE' has not been declared
  146. ERROR:HDLCompilers:28 - "mor1kx_immu.v" line 287 'TLB_IDLE' has not been declared
  147. ERROR:HDLCompilers:28 - "mor1kx_immu.v" line 300 'TLB_IDLE' has not been declared
  148. ERROR:HDLCompilers:28 - "mor1kx_immu.v" line 325 'TLB_IDLE' has not been declared
  149. ERROR:HDLCompilers:28 - "mor1kx_immu.v" line 348 'TLB_IDLE' has not been declared
  150. ERROR:HDLCompilers:28 - "mor1kx_immu.v" line 379 'TLB_IDLE' has not been declared
  151. ERROR:HDLCompilers:28 - "mor1kx_immu.v" line 383 'TLB_IDLE' has not been declared
  152. Module <mor1kx_immu> compiled
  153. ERROR:HDLCompilers:26 - "mor1kx_immu.v" line 387 expecting 'endmodule', found 'end'
  154. Compiling verilog file "mor1kx_icache.v" in library work
  155. Compiling verilog include file "mor1kx-defines.v"
  156. Compiling verilog include file "mor1kx-sprs.v"
  157. Compiling verilog file "mor1kx_dmmu.v" in library work
  158. Compiling verilog include file "mor1kx-defines.v"
  159. Compiling verilog include file "mor1kx-sprs.v"
  160. Module <mor1kx_icache> compiled
  161. ERROR:HDLCompilers:26 - "mor1kx_dmmu.v" line 270 unexpected token: 'localparam'
  162. ERROR:HDLCompilers:26 - "mor1kx_dmmu.v" line 270 unexpected token: 'TLB_IDLE'
  163. ERROR:HDLCompilers:26 - "mor1kx_dmmu.v" line 270 expecting 'endgenerate', found '2'
  164. ERROR:HDLCompilers:28 - "mor1kx_dmmu.v" line 275 'TLB_IDLE' has not been declared
  165. ERROR:HDLCompilers:28 - "mor1kx_dmmu.v" line 281 'TLB_IDLE' has not been declared
  166. ERROR:HDLCompilers:28 - "mor1kx_dmmu.v" line 295 'TLB_IDLE' has not been declared
  167. ERROR:HDLCompilers:28 - "mor1kx_dmmu.v" line 320 'TLB_IDLE' has not been declared
  168. ERROR:HDLCompilers:28 - "mor1kx_dmmu.v" line 343 'TLB_IDLE' has not been declared
  169. ERROR:HDLCompilers:28 - "mor1kx_dmmu.v" line 376 'TLB_IDLE' has not been declared
  170. ERROR:HDLCompilers:28 - "mor1kx_dmmu.v" line 380 'TLB_IDLE' has not been declared
  171. ERROR:HDLCompilers:28 - "mor1kx_dmmu.v" line 385 'TLB_IDLE' has not been declared
  172. Module <mor1kx_dmmu> compiled
  173. ERROR:HDLCompilers:26 - "mor1kx_dmmu.v" line 388 expecting 'endmodule', found 'end'
  174. Compiling verilog file "mor1kx_dcache.v" in library work
  175. Compiling verilog include file "mor1kx-defines.v"
  176. Compiling verilog include file "mor1kx-sprs.v"
  177. Compiling verilog file "mor1kx_cfgrs.v" in library work
  178. Compiling verilog include file "mor1kx-defines.v"
  179. Compiling verilog include file "mor1kx-sprs.v"
  180. Module <mor1kx_dcache> compiled
  181. Compiling verilog file "uart_transmitter.v" in library work
  182. Compiling verilog include file "uart_defines.v"
  183. Module <mor1kx_cfgrs> compiled
  184. Compiling verilog file "uart_sync_flops.v" in library work
  185. Compiling verilog include file "timescale.v"
  186. Module <uart_transmitter> compiled
  187. Compiling verilog file "uart_receiver.v" in library work
  188. Compiling verilog include file "uart_defines.v"
  189. Module <uart_sync_flops> compiled
  190. Compiling verilog file "syncreg.v" in library work
  191. Module <uart_receiver> compiled
  192. Compiling verilog file "mor1kx_wb_mux_espresso.v" in library work
  193. Compiling verilog include file "mor1kx-defines.v"
  194. Compiling verilog include file "mor1kx-sprs.v"
  195. Module <syncreg> compiled
  196. Compiling verilog file "mor1kx_wb_mux_cappuccino.v" in library work
  197. Compiling verilog include file "mor1kx-defines.v"
  198. Compiling verilog include file "mor1kx-sprs.v"
  199. Module <mor1kx_wb_mux_espresso> compiled
  200. Compiling verilog file "mor1kx_rf_espresso.v" in library work
  201. Compiling verilog include file "mor1kx-defines.v"
  202. Compiling verilog include file "mor1kx-sprs.v"
  203. Module <mor1kx_wb_mux_cappuccino> compiled
  204. Compiling verilog file "mor1kx_rf_cappuccino.v" in library work
  205. Compiling verilog include file "mor1kx-defines.v"
  206. Compiling verilog include file "mor1kx-sprs.v"
  207. Module <mor1kx_rf_espresso> compiled
  208. Compiling verilog include file "mor1kx_utils.vh"
  209. Compiling verilog file "mor1kx_lsu_espresso.v" in library work
  210. Compiling verilog include file "mor1kx-defines.v"
  211. Compiling verilog include file "mor1kx-sprs.v"
  212. Module <mor1kx_rf_cappuccino> compiled
  213. Compiling verilog file "mor1kx_lsu_cappuccino.v" in library work
  214. Compiling verilog include file "mor1kx-defines.v"
  215. Compiling verilog include file "mor1kx-sprs.v"
  216. Module <mor1kx_lsu_espresso> compiled
  217. Compiling verilog file "mor1kx_fetch_tcm_prontoespresso.v" in library work
  218. Compiling verilog include file "mor1kx-defines.v"
  219. Compiling verilog include file "mor1kx-sprs.v"
  220. Module <mor1kx_lsu_cappuccino> compiled
  221. Compiling verilog file "mor1kx_fetch_prontoespresso.v" in library work
  222. Compiling verilog include file "mor1kx-defines.v"
  223. Compiling verilog include file "mor1kx-sprs.v"
  224. Module <mor1kx_fetch_tcm_prontoespresso> compiled
  225. ERROR:HDLCompilers:26 - "mor1kx_fetch_prontoespresso.v" line 482 expecting 'end', found 'localparam'
  226. ERROR:HDLCompilers:26 - "mor1kx_fetch_prontoespresso.v" line 482 unexpected token: '='
  227. ERROR:HDLCompilers:26 - "mor1kx_fetch_prontoespresso.v" line 482 expecting 'endgenerate', found '('
  228. ERROR:HDLCompilers:26 - "mor1kx_fetch_prontoespresso.v" line 482 unexpected token: ')'
  229. ERROR:HDLCompilers:28 - "mor1kx_fetch_prontoespresso.v" line 485 'NUMBER_MINI_CACHE_WORDS' has not been declared
  230. ERROR:HDLCompilers:28 - "mor1kx_fetch_prontoespresso.v" line 488 'NUMBER_MINI_CACHE_WORDS' has not been declared
  231. ERROR:HDLCompilers:27 - "mor1kx_fetch_prontoespresso.v" line 488 Illegal redeclaration of 'mini_cache'
  232. ERROR:HDLCompilers:28 - "mor1kx_fetch_prontoespresso.v" line 489 'NUMBER_MINI_CACHE_WORDS' has not been declared
  233. Module <mor1kx_fetch_prontoespresso> compiled
  234. ERROR:HDLCompilers:26 - "mor1kx_fetch_prontoespresso.v" line 516 expecting 'endmodule', found 'for'
  235. Compiling verilog file "mor1kx_fetch_espresso.v" in library work
  236. Compiling verilog include file "mor1kx-defines.v"
  237. Compiling verilog include file "mor1kx-sprs.v"
  238. Compiling verilog file "mor1kx_fetch_cappuccino.v" in library work
  239. Compiling verilog include file "mor1kx-defines.v"
  240. Compiling verilog include file "mor1kx-sprs.v"
  241. Module <mor1kx_fetch_espresso> compiled
  242. Compiling verilog file "mor1kx_execute_ctrl_cappuccino.v" in library work
  243. Compiling verilog include file "mor1kx-defines.v"
  244. Compiling verilog include file "mor1kx-sprs.v"
  245. Module <mor1kx_fetch_cappuccino> compiled
  246. Compiling verilog file "mor1kx_execute_alu.v" in library work
  247. Compiling verilog include file "mor1kx-defines.v"
  248. Compiling verilog include file "mor1kx-sprs.v"
  249. Module <mor1kx_execute_ctrl_cappuccino> compiled
  250. Compiling verilog file "mor1kx_decode_execute_cappuccino.v" in library work
  251. Compiling verilog include file "mor1kx-defines.v"
  252. Compiling verilog include file "mor1kx-sprs.v"
  253. Module <mor1kx_execute_alu> compiled
  254. Compiling verilog file "mor1kx_decode.v" in library work
  255. Compiling verilog include file "mor1kx-defines.v"
  256. Compiling verilog include file "mor1kx-sprs.v"
  257. Module <mor1kx_decode_execute_cappuccino> compiled
  258. Compiling verilog file "mor1kx_ctrl_prontoespresso.v" in library work
  259. Compiling verilog include file "mor1kx-defines.v"
  260. Compiling verilog include file "mor1kx-sprs.v"
  261. Module <mor1kx_decode> compiled
  262. Compiling verilog file "mor1kx_ctrl_espresso.v" in library work
  263. Compiling verilog include file "mor1kx-defines.v"
  264. Compiling verilog include file "mor1kx-sprs.v"
  265. Module <mor1kx_ctrl_prontoespresso> compiled
  266. Compiling verilog file "mor1kx_ctrl_cappuccino.v" in library work
  267. Compiling verilog include file "mor1kx-defines.v"
  268. Compiling verilog include file "mor1kx-sprs.v"
  269. Module <mor1kx_ctrl_espresso> compiled
  270. Compiling verilog file "mor1kx_branch_prediction.v" in library work
  271. Compiling verilog include file "mor1kx-defines.v"
  272. Compiling verilog include file "mor1kx-sprs.v"
  273. Module <mor1kx_ctrl_cappuccino> compiled
  274. Compiling verilog file "bytefifo.v" in library work
  275. Module <mor1kx_branch_prediction> compiled
  276. Compiling verilog file "wb_bfm_slave.v" in library work
  277. Module <bytefifo> compiled
  278. Compiling verilog include file "wb_bfm_common.v"
  279. Compiling verilog include file "wb_bfm_params.v"
  280. Compiling verilog file "uart_wb.v" in library work
  281. Compiling verilog include file "uart_defines.v"
  282. Module <wb_bfm_slave> compiled
  283. Compiling verilog file "uart_regs.v" in library work
  284. Compiling verilog include file "uart_defines.v"
  285. Module <uart_wb> compiled
  286. Compiling verilog file "mor1kx_cpu_prontoespresso.v" in library work
  287. Compiling verilog include file "mor1kx-defines.v"
  288. Compiling verilog include file "mor1kx-sprs.v"
  289. Module <uart_regs> compiled
  290. Compiling verilog file "mor1kx_cpu_espresso.v" in library work
  291. Compiling verilog include file "mor1kx-defines.v"
  292. Compiling verilog include file "mor1kx-sprs.v"
  293. Module <mor1kx_cpu_prontoespresso> compiled
  294. Compiling verilog file "mor1kx_cpu_cappuccino.v" in library work
  295. Compiling verilog include file "mor1kx-defines.v"
  296. Compiling verilog include file "mor1kx-sprs.v"
  297. Module <mor1kx_cpu_espresso> compiled
  298. Compiling verilog file "arbiter.v" in library work
  299. Compiling verilog include file "verilog_utils.vh"
  300. Module <mor1kx_cpu_cappuccino> compiled
  301. ERROR:HDLCompilers:26 - "verilog_utils.vh" line 41 expecting 'EOF', found 'function'
  302. Compiling verilog file "adbg_wb_biu.v" in library work
  303. Compiling verilog include file "adbg_wb_defines.v"
  304. Compiling verilog file "adbg_or1k_status_reg.v" in library work
  305. Compiling verilog include file "adbg_or1k_defines.v"
  306. Compiling verilog file "adbg_or1k_biu.v" in library work
  307. Compiling verilog file "adbg_jsp_biu.v" in library work
  308. Compiling verilog file "adbg_crc32.v" in library work
  309. Compiling verilog file "wb_mux.v" in library work
  310. Compiling verilog include file "verilog_utils.vh"
  311. Compiling verilog file "wb_data_resize.v" in library work
  312. Compiling verilog file "wb_arbiter.v" in library work
  313. Compiling verilog include file "verilog_utils.vh"
  314. Compiling verilog file "uart_top.v" in library work
  315. Compiling verilog include file "uart_defines.v"
  316. Compiling verilog file "uart16550_model.v" in library work
  317. Compiling verilog include file "wb_bfm_params.v"
  318. Compiling verilog file "mor1kx_cpu.v" in library work
  319. Compiling verilog include file "mor1kx-defines.v"
  320. Compiling verilog include file "mor1kx-sprs.v"
  321. Compiling verilog file "mor1kx_bus_if_wb32.v" in library work
  322. Compiling verilog include file "mor1kx-defines.v"
  323. Compiling verilog include file "mor1kx-sprs.v"
  324. Compiling verilog file "mor1kx_bus_if_avalon.v" in library work
  325. Compiling verilog include file "mor1kx-defines.v"
  326. Compiling verilog include file "mor1kx-sprs.v"
  327. Compiling verilog file "adbg_wb_module.v" in library work
  328. Compiling verilog include file "adbg_defines.v"
  329. Compiling verilog include file "adbg_wb_defines.v"
  330. Compiling verilog file "adbg_or1k_module.v" in library work
  331. Compiling verilog include file "adbg_defines.v"
  332. Compiling verilog include file "adbg_or1k_defines.v"
  333. Compiling verilog file "adbg_jsp_module.v" in library work
  334. Compiling verilog include file "adbg_defines.v"
  335. Compiling verilog file "wb_uart_wrapper.v" in library work
  336. Compiling verilog file "wb_intercon.v" in library work
  337. Compiling verilog file "ram_wb_b3.v" in library work
  338. Compiling verilog file "mor1kx.v" in library work
  339. Compiling verilog include file "mor1kx-defines.v"
  340. Compiling verilog include file "mor1kx-sprs.v"
  341. Compiling verilog file "adbg_top.v" in library work
  342. Compiling verilog include file "adbg_defines.v"
  343. Compiling verilog file "orpsoc_top.v" in library work
  344. Compiling verilog include file "wb_intercon.vh"
  345. Analysis of file <"orpsoc_top.prj"> failed.
  346. -->
  347.  
  348.  
  349. Total memory usage is 496500 kilobytes
  350.  
  351. Number of errors : 33 ( 0 filtered)
  352. Number of warnings : 0 ( 0 filtered)
  353. Number of infos : 0 ( 0 filtered)
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