GC Readcommands (X-HDL conversion)

always @(DIHSTRB or DIDIR or DIRSTB or Cover_s or IO_READ or cmd)
begin : readcommands
   reg[3:0] i;
   reg latch;
   // <<X-HDL>> : Warning - VHDL and Verilog handle variable initialization differently
   //             The following statement probably requires hand modification.
   i = 0;
// <<X-HDL>> : Warning - VHDL and Verilog handle variable initialization differently
//             The following statement probably requires hand modification.
latch = 1'b0;
if (DIRSTB == 1'b0)
begin
   cmd[0] <= 8'h00 ;
   i = 0;
end
else if (DIHSTRB == 1'b1)
begin
   if (DIDIR == 1'b0)
   begin
      cmd[i] <= DID ;
      if (i < 12)
      begin
         i = i + 1;
      end
   end
   else
   begin
      i = 0;
   end
end
if (DIRSTB == 1'b0)
begin
   LBA_offset <= {32{1'b0}} ;
   latch = 1'b0;
end
else if ({cmd[0], cmd[1], cmd[2], cmd[3]} == 32'hAABBCCDD)
begin
   if (DIDIR == 1'b1 & latch == 1'b0)
   begin
      LBA_offset <= {cmd[8], cmd[9], cmd[10], cmd[11]} ;
      latch = 1'b1;
   end
end
if (DIDIR == 1'b1)
begin
   if (Cover_s == 1'b0)
   begin
      DIERRB <= 1'b1 ;
   end
   else
   begin
      if (cmd[0] == 8'hE0)
      begin
         DIERRB <= 1'b1 ;
      end
      else
      begin
         DIERRB <= 1'b0 ;
         end
      end
   end
   else
   begin
      DIERRB <= 1'b1 ;
   end
   if (DIDIR == 1'b0 & i < 10)
   begin
      DIDSTRB <= 1'b0 ;
   end
   else
   begin
      DIDSTRB <= IO_READ ;
   end
end