Entity MicroprogramController is
		port (
		RESET: in std_logic;
		CLK: in std_logic;
		Address_In: in std_logic_vector ( 7 downto 0);
		Address_Out: out std_logic_vector ( 7 downto 0)
		Instruction_In: in std_logic_vector (15 downto 0);
		Constant_Out: out std_logic_vector ( 7 downto 0)
		V,C,N,Z: in std_logic;
		DX,AX,BX,,FS: out std_logic_vector ( 3 downto 0);
		MB,MD,RW,MM,MW: out std_logic
			);
	End MicroprogramController;

	Architecture MCU_Behavorial of MicroprogramController is
	Begin

	-- Portmap convention: "Inputs listed first in order of appearance.
	-- 						Then, outputs listed in order of appearance."

	U1: entity WORK.InstructionDecoderController PORT MAP
	(	RESET =>, CLK=>, IR=>, V=>, C=>, 				-- Input
		N=>, Z=>, MB=>, MD=>, RW=>, MM=>, MW=>,			--

		PS=>, IL=>, DX=>, AX=>, BX=>, FS=>				-- Output
	);


	U2: entity WORK.InstructionRegister PORT MAP
	(	RESET=>, CLK=>, Instruction_In=>, IL=>, 		-- Input

		IR=>											-- Output
	);


	U3: entity WORK.MicroprogramController PORT MAP
	(	RESET=>, CLK=>, Address_In=>, Instruction_In=>, V=>, C=>, N=>, Z=>,	--Input

		Address_Out=>, Constant_Out=>, DX=>, AX=>, BX=>, FS=>, MB=>, MD=>, 	--Output
		RW=>, MM=>, MW=>
	);


	U4: entity WORK.SignExtender PORT MAP
	(	IR =>,					-- Input

		Extended_8=> 			-- Output
	);


	U5: entity WORK.ZeroFiller PORT MAP
	(	IR=>, 					-- Input

		Zero_Filled_9=>			-- Output
	);

	End;