library ieee;
use ieee.std_logic_1164.all;

entity xor_gate is
port(
        a : in std_logic;
        b : in std_logic;
        pari : in std_logic;
        paro : out std_logic);

    end xor_gate;

architecture behavior of xor_gate is
    begin

    paro <= (a xor b) or pari;

end behavior;

library ieee;
use ieee.std_logic_1164.all;
entity parity_2 is

port(a: in std_logic_vector (0 to 15);
      b: in std_logic_vector (0 to 15);
      paro: out std_logic);

end parity_2;

architecture behavior of parity_2 is
        signal parry: std_logic_vector (0 to 15);

component xor_gate
            port (a,b: in std_logic;
                   pari: in std_logic;
                    paro: out std_logic);

end component;

begin

c1: xor_gate port map (a(0), b(0), '0', parry(0));
c: for i in 1 to 15 generate
c2: xor_gate port map (parry(i-1), a(i), b(i), parry(i));

end generate;

paro <= parry(15);

end behavior;