Makefile

CC ?= gcc
CFLAGS = -ansi -Wall -pedantic
#
OBJS = file1.o file2.o file3.o
PROG = my_program
#
#
all : $(PROG)

$(PROG) : $(OBJS)
   $(CC) $(LDFLAGS) $(LDLIBS) $^ -o $@

clean :
   $(RM) *.o $(PROG) *.*~

# For GNU Make, I believe harmless in other versions
.PHONY: clean