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- --Robin Gonzalez. código en VHDL de una maquina de estados para un sistema de alarma, implementado en un GAL22v10
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_arith.all;
- entity alarm is port (
- clk: in std_logic;
- a: in std_logic_vector(3 downto 0);
- b: in std_logic_vector(3 downto 0);
- ledOn: out std_logic;
- x: out std_logic_vector(1 downto 0));
- attribute pin_numbers of alarm: entity is
- --inputs
- "b(0):6 b(1):5 b(2):4 b(3):3 "
- &
- "a(0):10 a(1):9 a(2):8 a(3):7 "
- --outputs
- &
- "x(0):15 x(1):16 "
- &
- "ledOn:17";
- end alarm;
- architecture arch_alarm of alarm is
- type states is (state0, state1, state2, state3 );
- signal stado_pres, stado_fut: states;
- --type boolean is (true, false);
- --signal vdd: boolean;
- begin
- p_estados: process(stado_pres,a,b) begin
- case stado_pres is
- when state0 =>
- x <= "00";
- ledOn <= '0';
- if a = NOT(b) then
- stado_fut <= state1;
- else
- stado_fut <= state0;
- end if;
- when state1 =>
- x <= "01";
- if a = NOT(b) then
- stado_fut <= state2;
- else
- stado_fut <= state0;
- end if;
- when state2 =>
- x <= "10";
- if a = NOT(b) then
- stado_fut <= state3;
- else
- stado_fut <= state0;
- end if;
- when state3 =>
- x <= "11";
- if a = NOT(b) then
- ledOn <= '1';
- end if;
- stado_fut <= state0;
- end case;
- end process p_estados;
- p_reloj: process(clk) begin
- if(clk'event and clk= '1') then
- stado_pres <= stado_fut;
- end if;
- end process p_reloj;
- end arch_alarm;
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