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  1. RK3188 with 32bit memory bus
  2.  
  3. tinymembench v0.3.9 (simple benchmark for memory throughput and latency)
  4.  
  5. ==========================================================================
  6. == Memory bandwidth tests ==
  7. == ==
  8. == Note 1: 1MB = 1000000 bytes ==
  9. == Note 2: Results for 'copy' tests show how many bytes can be ==
  10. == copied per second (adding together read and writen ==
  11. == bytes would have provided twice higher numbers) ==
  12. == Note 3: 2-pass copy means that we are using a small temporary buffer ==
  13. == to first fetch data into it, and only then write it to the ==
  14. == destination (source -> L1 cache, L1 cache -> destination) ==
  15. == Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
  16. == brackets ==
  17. ==========================================================================
  18.  
  19. C copy backwards : 469.1 MB/s
  20. C copy : 883.3 MB/s (1.7%)
  21. C copy prefetched (32 bytes step) : 683.3 MB/s
  22. C copy prefetched (64 bytes step) : 684.8 MB/s (1.2%)
  23. C 2-pass copy : 796.2 MB/s
  24. C 2-pass copy prefetched (32 bytes step) : 737.6 MB/s (1.5%)
  25. C 2-pass copy prefetched (64 bytes step) : 735.2 MB/s (1.2%)
  26. C fill : 3069.5 MB/s
  27. ---
  28. standard memcpy : 1013.6 MB/s (2.2%)
  29. standard memset : 3071.3 MB/s
  30. ---
  31. NEON read : 1371.4 MB/s (1.0%)
  32. NEON read prefetched (32 bytes step) : 1854.8 MB/s
  33. NEON read prefetched (64 bytes step) : 1903.1 MB/s (1.7%)
  34. NEON read 2 data streams : 1571.6 MB/s
  35. NEON read 2 data streams prefetched (32 bytes step) : 2161.9 MB/s (1.9%)
  36. NEON read 2 data streams prefetched (64 bytes step) : 2353.7 MB/s
  37. NEON copy : 609.4 MB/s (4.3%)
  38. NEON copy prefetched (32 bytes step) : 1102.6 MB/s (1.4%)
  39. NEON copy prefetched (64 bytes step) : 950.9 MB/s
  40. NEON unrolled copy : 912.5 MB/s (1.4%)
  41. NEON unrolled copy prefetched (32 bytes step) : 1021.9 MB/s
  42. NEON unrolled copy prefetched (64 bytes step) : 998.1 MB/s
  43. NEON copy backwards : 339.4 MB/s (0.2%)
  44. NEON copy backwards prefetched (32 bytes step) : 746.0 MB/s
  45. NEON copy backwards prefetched (64 bytes step) : 811.9 MB/s (1.2%)
  46. NEON 2-pass copy : 769.4 MB/s
  47. NEON 2-pass copy prefetched (32 bytes step) : 1039.7 MB/s
  48. NEON 2-pass copy prefetched (64 bytes step) : 1022.0 MB/s (1.3%)
  49. NEON unrolled 2-pass copy : 775.2 MB/s (1.0%)
  50. NEON unrolled 2-pass copy prefetched (32 bytes step) : 1029.0 MB/s
  51. NEON unrolled 2-pass copy prefetched (64 bytes step) : 1067.7 MB/s (1.5%)
  52. NEON fill : 3070.4 MB/s (1.0%)
  53. NEON fill backwards : 3071.9 MB/s (1.1%)
  54. VFP copy : 907.3 MB/s (1.0%)
  55. VFP 2-pass copy : 845.9 MB/s
  56. ARM fill (STRD) : 3071.0 MB/s
  57. ARM fill (STM with 8 registers) : 3070.8 MB/s (1.0%)
  58. ARM fill (STM with 4 registers) : 3071.6 MB/s (1.8%)
  59. ARM copy prefetched (incr pld) : 1050.2 MB/s
  60. ARM copy prefetched (wrap pld) : 1052.0 MB/s
  61. ARM 2-pass copy prefetched (incr pld) : 1044.6 MB/s (1.6%)
  62. ARM 2-pass copy prefetched (wrap pld) : 1051.4 MB/s (1.0%)
  63.  
  64. ==========================================================================
  65. == Memory latency test ==
  66. == ==
  67. == Average time is measured for random memory accesses in the buffers ==
  68. == of different sizes. The larger is the buffer, the more significant ==
  69. == are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
  70. == accesses. For extremely large buffer sizes we are expecting to see ==
  71. == page table walk with several requests to SDRAM for almost every ==
  72. == memory access (though 64MiB is not nearly large enough to experience ==
  73. == this effect to its fullest). ==
  74. == ==
  75. == Note 1: All the numbers are representing extra time, which needs to ==
  76. == be added to L1 cache latency. The cycle timings for L1 cache ==
  77. == latency can be usually found in the processor documentation. ==
  78. == Note 2: Dual random read means that we are simultaneously performing ==
  79. == two independent memory accesses at a time. In the case if ==
  80. == the memory subsystem can't handle multiple outstanding ==
  81. == requests, dual random read has the same timings as two ==
  82. == single reads performed one after another. ==
  83. ==========================================================================
  84.  
  85. block size : single random read / dual random read
  86. 1024 : 0.0 ns / 0.0 ns
  87. 2048 : 0.0 ns / 0.0 ns
  88. 4096 : 0.0 ns / 0.0 ns
  89. 8192 : 0.0 ns / 0.0 ns
  90. 16384 : 0.0 ns / 0.0 ns
  91. 32768 : 0.0 ns / 0.0 ns
  92. 65536 : 8.2 ns / 12.9 ns
  93. 131072 : 12.2 ns / 16.6 ns
  94. 262144 : 16.8 ns / 20.8 ns
  95. 524288 : 22.5 ns / 27.5 ns
  96. 1048576 : 86.3 ns / 131.3 ns
  97. 2097152 : 116.7 ns / 167.6 ns
  98. 4194304 : 133.2 ns / 184.6 ns
  99. 8388608 : 144.1 ns / 199.9 ns
  100. 16777216 : 155.0 ns / 212.3 ns
  101. 33554432 : 165.1 ns / 226.1 ns
  102. 67108864 : 178.9 ns / 251.2 ns
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