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-- Company:
-- Engineer:
--
-- Create Date:    17:40:15 06/19/2010
-- Design Name:
-- Module Name:    UART_RX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity UART_RX is
    Port ( CLK : in  STD_LOGIC;
           RX_PIN : in  STD_LOGIC;
           OUTPUT : out integer range 0 to 255;
              POP : out STD_LOGIC);
end UART_RX;

architecture Behavioral of UART_RX is
    SIGNAL bit_cnt : integer range 0 to 12;
    SIGNAL outbuf  : STD_LOGIC_VECTOR (8 downto 1);
begin
    PROCESS ( CLK )
    BEGIN
        IF RISING_EDGE(CLK) THEN
            CASE bit_cnt IS
                WHEN 0 =>
                    IF RX_PIN = '0' THEN
                        bit_cnt <= bit_cnt + 1;
                    END IF;
                WHEN 9 =>
                    bit_cnt <= bit_cnt + 1;
                    POP <= '1';
                WHEN 10 =>
                    POP <= '0';
                    bit_cnt <= 0;
                WHEN OTHERS =>
                    outbuf(bit_cnt) <= RX_PIN;
                    bit_cnt <= bit_cnt + 1;
            END CASE;
        END IF;
    END PROCESS;

    OUTPUT <= conv_integer(outbuf);
end Behavioral;