API tools faq
paste
Advertisement
Guest User

VybridLpddr2.ds

a guest
Apr 15th, 2016
90
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 9.59 KB | None | 0 0
raw download clone embed print report
  1. # reset to known state
  2. reset
  3. pause 100
  4.  
  5. # initialise ecc on ocram. uncomment to perform ecc check.
  6. #memory set 0x3f000000++0x3ffff %quad 0xffffffff #sysram0
  7. #memory set 0x3f040000++0x3ffff %quad 0xffffffff #sysram1
  8.  
  9. memory 0x40048220 0x400ae4d0 noverify
  10.  
  11. # select pll as system clock
  12. memory set 0x4006b02c 0 0x78 # power up fxosc
  13. # wait ((data.long(0x4006b004))&0x20)==0x20 #wait for fxosc to lock
  14. pause 500ms
  15. memory set 0x4006b008 0 0x20 # set fxosc as fast clock
  16.  
  17. # enable all clocks gates from ccm
  18. memory set 0x4006b040 0 0xffffffff
  19. memory set 0x4006b044 0 0xffffffff
  20. memory set 0x4006b048 0 0xffffffff
  21. memory set 0x4006b04c 0 0xffffffff
  22. memory set 0x4006b050 0 0xffffffff
  23. memory set 0x4006b054 0 0xffffffff
  24. memory set 0x4006b058 0 0xffffffff
  25. memory set 0x4006b05c 0 0xffffffff
  26. memory set 0x4006b060 0 0xffffffff
  27. memory set 0x4006b064 0 0xffffffff
  28. memory set 0x4006b068 0 0xffffffff
  29. memory set 0x4006b06c 0 0xffffffff
  30.  
  31. memory set 0x40050270 0 0x2001 # pll1
  32. # wait ((data.long(0x40050270))&0x80000000)==0x80000000 #wait for lock
  33. pause 500ms
  34. memory set 0x40050030 0 0x2001 # pll2
  35. # wait ((data.long(40050030))&0x80000000)==0x80000000 #wait for lock
  36. pause 500ms
  37. memory set 0x40050010 0 0x3040 # pll3
  38. # wait ((data.long(40050010))&0x80000000)==0x80000000 #wait for lock
  39. pause 500ms
  40.  
  41. memory set 0x40050070 0 0x00002031 # anadig_pll_audio_ctrl: pll4
  42. pause 500ms
  43. memory set 0x400500e0 0 0x00002001 # anadig_pll_enet_ctrl: pll5
  44. pause 500ms
  45. memory set 0x400500a0 0 0x00002028 # anadig_pll_video_ctrl: pll6
  46. pause 500ms
  47. # wait ((data.long(0x400502c0))&0xff)==0x7c #wait for lock
  48.  
  49.  
  50. # enable all pfds sources and set sysclk as pll1 pfd3 for 396mhz
  51.  
  52. memory set 0x4006b000 0 0x00010005 # ccm_ccr: firc_en=1 and oscnt=5
  53. memory set 0x4006b008 0 0x0003ff24 # ccm_ccsr: pll1 uses pll1_pfd3, enable all pll1 and pll2, select fast clock, and sys_clock_sel use pll1
  54. memory set 0x4006b00c 0 0x00000850 # ccm_cacrr: arm_div=0 (div by 1), bus_div=2 (div by 3), ipg_div value is 1 (div by 2), pll4 value is 1 (div 4)
  55.  
  56.  
  57. #########################################################################
  58. ### ddr_iomuxvoid
  59. #########################################################################
  60.  
  61. memory set 0x400482B0 0 0x00000140 # VF610_PAD_DDR_D2__DDR_D_2
  62. memory set 0x4004825C 0 0x00000140 # VF610_PAD_DDR_A0__DDR_A_0
  63. memory set 0x40048240 0 0x00000140 # VF610_PAD_DDR_A7__DDR_A_7
  64. memory set 0x400482A0 0 0x00000140 # VF610_PAD_DDR_D6__DDR_D_6
  65. memory set 0x4004827C 0 0x00000140 # VF610_PAD_DDR_D15__DDR_D_15
  66. memory set 0x400482BC 0 0x00000140 # VF610_PAD_DDR_DQM1__DDR_DQM_1
  67. memory set 0x400482C0 0 0x00000140 # VF610_PAD_DDR_DQM0__DDR_DQM_0
  68. memory set 0x40048258 0 0x00000140 # VF610_PAD_DDR_A12__DDR_A_12
  69. memory set 0x40048244 0 0x00000140 # VF610_PAD_DDR_A6__DDR_A_6
  70. memory set 0x40048290 0 0x00000140 # VF610_PAD_DDR_D10__DDR_D_10
  71. memory set 0x40048294 0 0x00000140 # VF610_PAD_DDR_D9__DDR_D_9
  72. memory set 0x400482B8 0 0x00000140 # VF610_PAD_DDR_D0__DDR_D_0
  73. memory set 0x4004828C 0 0x00000140 # VF610_PAD_DDR_D11__DDR_D_11
  74. memory set 0x40048298 0 0x00000140 # VF610_PAD_DDR_D8__DDR_D_8
  75. memory set 0x40048280 0 0x00000140 # VF610_PAD_DDR_D14__DDR_D_14
  76. memory set 0x40048284 0 0x00000140 # VF610_PAD_DDR_D13__DDR_D_13
  77. memory set 0x4004823C 0 0x00000140 # VF610_PAD_DDR_A8__DDR_A_8
  78. memory set 0x400482C8 0 0x0001014c # VF610_PAD_DDR_DQS0__DDR_DQS_0
  79. memory set 0x400482C4 0 0x0001014c # VF610_PAD_DDR_DQS1__DDR_DQS_1
  80. memory set 0x40048248 0 0x00000140 # VF610_PAD_DDR_A5__DDR_A_5
  81. memory set 0x400482A4 0 0x00000140 # VF610_PAD_DDR_D5__DDR_D_5
  82. memory set 0x40048274 0 0x00010140 # VF610_PAD_DDR_CLK__DDR_CLK_0
  83. memory set 0x40048288 0 0x00000140 # VF610_PAD_DDR_D12__DDR_D_12
  84. memory set 0x4004824C 0 0x00000140 # VF610_PAD_DDR_A4__DDR_A_4
  85. memory set 0x40048250 0 0x00000140 # VF610_PAD_DDR_A3__DDR_A_3
  86. memory set 0x40048270 0 0x00000140 # VF610_PAD_DDR_CKE__DDR_CKE_0
  87. memory set 0x40048254 0 0x00000140 # VF610_PAD_DDR_A12__DDR_A_2
  88. memory set 0x400482AC 0 0x00000140 # VF610_PAD_DDR_D3__DDR_D_3
  89. memory set 0x40048278 0 0x00000140 # VF610_PAD_DDR_CS__DDR_CS_B_0
  90. memory set 0x40048238 0 0x00000140 # VF610_PAD_DDR_A9__DDR_A_9
  91. memory set 0x400482A8 0 0x00000140 # VF610_PAD_DDR_D4__DDR_D_4
  92. memory set 0x400482B4 0 0x00000140 # VF610_PAD_DDR_D1__DDR_D_1
  93. memory set 0x4004829C 0 0x00000140 # VF610_PAD_DDR_D7__DDR_D_7
  94.  
  95.  
  96. #########################################################################
  97.  
  98.  
  99. #########################################################################
  100. ### ddr_init2
  101. #########################################################################
  102.  
  103. memory set 0x400AE000 0 0x00000500 # DDRMC_CR00
  104. memory set 0x400AE008 0 0x00000028 # DDRMC_CR02
  105. memory set 0x400AE00C 0 0x00013880 # DDRMC_CR03
  106. memory set 0x400AE010 0 0x00000190 # DDRMC_CR04
  107. memory set 0x400AE014 0 0x00000fa0 # DDRMC_CR05
  108. memory set 0x400AE030 0 0x00000306 # DDRMC_CR12
  109. memory set 0x400AE034 0 0x18040202 # DDRMC_CR13
  110. memory set 0x400AE038 0 0x14110311 # DDRMC_CR14
  111. memory set 0x400AE040 0 0x05030000 # DDRMC_CR16
  112. memory set 0x400AE044 0 0x006d6005 # DDRMC_CR17
  113. memory set 0x400AE048 0 0x00000603 # DDRMC_CR18
  114. memory set 0x400AE050 0 0x01000000 # DDRMC_CR20
  115. memory set 0x400AE054 0 0x00070101 # DDRMC_CR21
  116. memory set 0x400AE058 0 0x000e0000 # DDRMC_CR22
  117. memory set 0x400AE05C 0 0x03020000 # DDRMC_CR23
  118. memory set 0x400AE060 0 0x00000008 # DDRMC_CR24
  119. memory set 0x400AE064 0 0x00010000 # DDRMC_CR25
  120. memory set 0x400AE068 0 0x0c300034 # DDRMC_CR26
  121. memory set 0x400AE070 0 0x00000005 # DDRMC_CR28
  122. memory set 0x400AE074 0 0x00000003 # DDRMC_CR29
  123. memory set 0x400AE078 0 0x0000000a # DDRMC_CR30
  124. memory set 0x400AE07C 0 0x00380038 # DDRMC_CR31
  125. memory set 0x400AE084 0 0x00010000 # DDRMC_CR33
  126. memory set 0x400AE088 0 0x02020200 # DDRMC_CR34
  127. memory set 0x400AE098 0 0x00000000 # DDRMC_CR38
  128. memory set 0x400AE09C 0 0x04001000 # DDRMC_CR39
  129. memory set 0x400AE0A4 0 0x00000001 # DDRMC_CR41
  130. memory set 0x400AE0B4 0 0x00000000 # DDRMC_CR45
  131. memory set 0x400AE0B8 0 0x00000000 # DDRMC_CR46
  132. memory set 0x400AE0BC 0 0x00000000 # DDRMC_CR47
  133. memory set 0x400AE0C0 0 0x00230000 # DDRMC_CR48
  134. memory set 0x400AE0C4 0 0x00000004 # DDRMC_CR49
  135. memory set 0x400AE0CC 0 0x00010000 # DDRMC_CR51
  136. memory set 0x400AE0D0 0 0x00000000 # DDRMC_CR52
  137. memory set 0x400AE0E4 0 0x00000000 # DDRMC_CR57
  138. memory set 0x400AE0E8 0 0x00000000 # DDRMC_CR58
  139. memory set 0x400AE108 0 0x00900190 # DDRMC_CR66
  140. memory set 0x400AE10C 0 0x00000024 # DDRMC_CR67
  141. memory set 0x400AE114 0 0x00000200 # DDRMC_CR69
  142. memory set 0x400AE118 0 0x00000080 # DDRMC_CR70
  143. memory set 0x400AE11C 0 0x00001400 # DDRMC_CR71
  144. memory set 0x400AE120 0 0x01000000 # DDRMC_CR72
  145. memory set 0x400AE124 0 0x0a010300 # DDRMC_CR73
  146. memory set 0x400AE128 0 0x0101ffff # DDRMC_CR74
  147. memory set 0x400AE12C 0 0x01010101 # DDRMC_CR75
  148. memory set 0x400AE130 0 0x03030101 # DDRMC_CR76
  149. memory set 0x400AE134 0 0x01000001 # DDRMC_CR77
  150. memory set 0x400AE138 0 0x0001000c # DDRMC_CR78
  151. memory set 0x400AE13C 0 0x01000000 # DDRMC_CR79
  152. memory set 0x400AE148 0 0x1fffffff # DDRMC_CR82
  153. memory set 0x400AE15C 0 0x01010000 # DDRMC_CR87
  154. memory set 0x400AE16C 0 0x03030300 # DDRMC_CR91
  155. memory set 0x400AE170 0 0x00010303 # DDRMC_CR92
  156. memory set 0x400AE180 0 0x00002819 # DDRMC_CR96
  157. memory set 0x400AE1A4 0 0x00202000 # DDRMC_CR105
  158. memory set 0x400AE1B8 0 0x00002020 # DDRMC_CR110
  159. memory set 0x400AE1C8 0 0x00000000 # DDRMC_CR114
  160. memory set 0x400AE1F4 0 0x00000000 # DDRMC_CR125
  161. memory set 0x400AE1F8 0 0x00000c00 # DDRMC_CR126
  162. memory set 0x400AE1FC 0 0x00000000 # DDRMC_CR127
  163. memory set 0x400AE20C 0 0x00000000 # DDRMC_CR131
  164. memory set 0x400AE210 0 0x00000305 # DDRMC_CR132
  165. memory set 0x400AE224 0 0x00020000 # DDRMC_CR137
  166. memory set 0x400AE268 0 0x68283000 # DDRMC_CR154
  167.  
  168.  
  169. #########################################################################
  170.  
  171. pause 100ms
  172.  
  173. #########################################################################
  174. ### ddr_phy_init2
  175. #########################################################################
  176.  
  177. memory set 0x400AE400 0 0x00000027 # DDRMC_PHY00
  178. memory set 0x400AE404 0 0x00000027 # DDRMC_PHY01
  179. memory set 0x400AE408 0 0x0038005a # DDRMC_PHY02
  180. memory set 0x400AE40C 0 0x00040404 # DDRMC_PHY03
  181. memory set 0x400AE410 0 0x00002700 # DDRMC_PHY04
  182. memory set 0x400AE440 0 0x00000027 # DDRMC_PHY16
  183. memory set 0x400AE444 0 0x00000027 # DDRMC_PHY17
  184. memory set 0x400AE448 0 0x0038005a # DDRMC_PHY18
  185. memory set 0x400AE44C 0 0x00040404 # DDRMC_PHY19
  186. memory set 0x400AE450 0 0x00002700 # DDRMC_PHY20
  187. memory set 0x400AE480 0 0x00000027 # DDRMC_PHY32
  188. memory set 0x400AE484 0 0x00000027 # DDRMC_PHY33
  189. memory set 0x400AE488 0 0x0038005a # DDRMC_PHY34
  190. memory set 0x400AE48C 0 0x00040404 # DDRMC_PHY35
  191. memory set 0x400AE490 0 0x00002700 # DDRMC_PHY36
  192. memory set 0x400AE4C4 0 0x00040007 # DDRMC_PHY49
  193. memory set 0x400AE4C8 0 0x00002900 # DDRMC_PHY50
  194. memory set 0x400AE4D0 0 0x00000000 # DDRMC_PHY52
  195.  
  196.  
  197. #########################################################################
  198.  
  199.  
  200. #########################################################################
  201. ### ddr_init2 end
  202. #########################################################################
  203.  
  204. pause 100ms
  205.  
  206. memory set 0x400ae0b4 0 0x01060000
  207.  
  208. ### pause 100ms
  209.  
  210. memory set 0x400ae148 0 0x1FFFFFFF
  211. memory set 0x400ae000 0 0x00000501
  212.  
  213. pause 100ms
  214. memory set 0x400ae114 0 0x00000102
  215.  
  216. pause 100ms
  217. #########################################################################
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!