process

data_conv : process (
    SYSCLK
    )
begin
    if (rising_edge(SYSCLK)) then
        if (reset(reset'left) ='1') then
        --  ACCEL_Z <= (others => '0');
        elsif( drdy ='1') then
            XX <= accel_x (11 downto 4);
            YY <= accel_y (11 downto 4);
            ZZ <= accel_z (11 downto 4);
        end if;
    end if;
end process data_conv;