Some unofficial features of the TMS chips

Some unofficial features of the TMS chips

Normally, screen 2 has three pattern and colour tables, one for the upper, middle and lower part of the screen.

The TMS9918 documentation specifies that pattern table base address (r#4) bits 0-1 and colour table base address (r#3) bits 0-6 should all be set to 1, but these actually act as masks.

On a Texas Instruments TMS9918 (it holds also for the other vdp variants TMS99XX):
pattern generator table (r#4) bits 0-1 mask which of the three pattern tables is used in each part
colour generator table (r#3) bits 5-6 mask which of the three colour tables is used for each part
colour generator table (r#3) bits 0-4 mask the pattern number

More in detail:
Bit 2 of register #4 sets the pattern generator address (it corresponds to bit 13 of the address, it's either address 0 or 2000h).
Bits 0 and 1 are an AND mask over the highest bits of the character number (10 bits in 0-767).
If bit 0 of control register #4 is set, the second array of 256 patterns in the pattern generator is used for the middle 8 rows of characters, otherwise the first 256 patterns. If bit 1 is set, the third array of patterns is used in the pattern generator , otherwise the first.

Bit 7 of register #3 sets the color generator address (it corresponds to bit 13 of the address, so it's either address 0 or 2000h).
Somewhat like control register #4 for the pattern generator, bits 6 - 0 are an AND mask over the top 7 bits of the character number during color generation.

A simple usage for this feature is to have a single pattern / colour table active on the entire screen by setting to 0 bits 5-6 in r#3 and bit 0-1 in r#4.
However, there is a side effect on the TMS9918 hardware (it is reported also on other TMS99XX vdp's): if you mask the pattern generator  table (r#4), sprites get messed up and you can only use sprites 0-7 out of 32. The other sprites experience a ghosting effect, they will appear tree times in the banks like their y coordinates where masked by 63 and displaced by 0, by 64 and by 128. Add that the ghosting effect is also very unstable, its entity varies with the chip temperature. This severely limits the use of this feature.

An interesting way to exploit the above features without incurring in sprite restrictions, is to sacrifice the use upper tile bank to gain two vram pages of screen 2 tiles for the remaining middle and lower banks.
The trick is to not mask pattern generator table (setting to 1 bits 0-1 in r#4 allows to use freely sprites), and to set to 0 bits 5-6 in r#3, so the upper color generator bank is used for the other two banks.
Provided that you fill the upper bank with a blank tile, you can show page 0 by setting the pattern generator table at 0x0000 (useful data will be at 0x800 and at 0x1000, up to 0x17FF) and color the generator table at 0x2000 (useful data will be in 0x2000-0x27FF).
Page 1 will instead be shown by setting the pattern generator table at 0x2000 (useful data will be at 0x2800 and at 0x3000, up to 0x38FF) and the color generator table at 0x0000 (useful data will be in 0x0000-0x07FF).

Apart the problem with the upper bank (hardly it can be used as the same data means color and pattern definitions in the two pages), the other issue is that the two lower banks of tiles share the same color generator table, anyway you get two screen 2 pages for double buffering and other tricks, doubling the amount of tiles to be used in each area.

NB: another issue is about the Texas Instruments TMS9118, where the colour table (r#3) bits 0-3 do not mask the pattern number.
Add also that on a Toshiba T6950 and Toshiba equivalent chips (TMS clones), the mirroring does not work at all. On this VDP only the top 1/3 of the screen will be shown correctly if the mirroring bits aren’t set to 1.
This clone is not commonly used, it is reported to be present in some revisions of the following MSX computers: Toshiba HX-10, Toshiba HX-20, Sony HB-10P
The sole emulator that (up to now) has implemented this difference between TMS and Toshiba clones is Meisei.

Yamaha chips V9938 / V9958 behave like the TMS9918.

References:

http://bifi.msxnet.org/msxnet/tech/tms9918a.txt
http://www.msx.org/forum/development/msx-development/new-hybrid-mode-found
http://atariage.com/forums/topic/168968-f18a/page-11?gopid=2219848
http://www.msx.org/forum/msx-talk/development/only-one-charset-screen2
http://www.msx.org/forum/development/msx-development/undocumented-mode-1-2-polldiscussion